Default to 8 PMPs; support 0 PMPs
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97006ab396
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17b1ee3037
@ -26,7 +26,7 @@ case class GroundTestTileParams(
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val icache = None
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val btb = None
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val rocc = Nil
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val core = rocket.RocketCoreParams() //TODO remove this
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val core = rocket.RocketCoreParams(nPMPs = 0) //TODO remove this
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val cached = if(dcache.isDefined) 1 else 0
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val dataScratchpadBytes = 0
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}
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@ -667,7 +667,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
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when (decoded_addr(CSRs.tdata2)) { bp.address := wdata }
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}
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}
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for (((pmp, next), i) <- (reg_pmp zip (reg_pmp.tail :+ reg_pmp.last)) zipWithIndex) {
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if (reg_pmp.nonEmpty) for (((pmp, next), i) <- (reg_pmp zip (reg_pmp.tail :+ reg_pmp.last)) zipWithIndex) {
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require(xLen % pmp.cfg.getWidth == 0)
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when (decoded_addr(CSRs.pmpcfg0 + pmpCfgIndex(i)) && !pmp.locked) {
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pmp.cfg := new PMPConfig().fromBits(wdata >> ((i * pmp.cfg.getWidth) % xLen))
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@ -136,7 +136,7 @@ class PMPChecker(lgMaxSize: Int)(implicit p: Parameters) extends CoreModule()(p)
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val x = Bool(OUTPUT)
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}
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val default = io.prv > PRV.S
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val default = if (io.pmp.isEmpty) true.B else io.prv > PRV.S
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val pmp0 = Wire(init = 0.U.asTypeOf(new PMP))
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pmp0.cfg.r := default
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pmp0.cfg.w := default
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@ -18,7 +18,7 @@ case class RocketCoreParams(
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useAtomics: Boolean = true,
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useCompressed: Boolean = true,
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nBreakpoints: Int = 1,
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nPMPs: Int = 16,
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nPMPs: Int = 8,
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nPerfCounters: Int = 0,
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nCustomMRWCSRs: Int = 0,
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mtvecInit: Option[BigInt] = Some(BigInt(0)),
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