From 17b1ee30370fb6cc0cec6ee51e5487d4d39f6fa0 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Fri, 24 Mar 2017 15:55:51 -0700
Subject: [PATCH] Default to 8 PMPs; support 0 PMPs

---
 src/main/scala/groundtest/Tile.scala | 2 +-
 src/main/scala/rocket/CSR.scala      | 2 +-
 src/main/scala/rocket/PMP.scala      | 2 +-
 src/main/scala/rocket/Rocket.scala   | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/main/scala/groundtest/Tile.scala b/src/main/scala/groundtest/Tile.scala
index 2114d4d5..7503533c 100644
--- a/src/main/scala/groundtest/Tile.scala
+++ b/src/main/scala/groundtest/Tile.scala
@@ -26,7 +26,7 @@ case class GroundTestTileParams(
   val icache = None
   val btb = None
   val rocc = Nil
-  val core = rocket.RocketCoreParams() //TODO remove this
+  val core = rocket.RocketCoreParams(nPMPs = 0) //TODO remove this
   val cached = if(dcache.isDefined) 1 else 0
   val dataScratchpadBytes = 0
 }
diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala
index f4a8d460..88cff329 100644
--- a/src/main/scala/rocket/CSR.scala
+++ b/src/main/scala/rocket/CSR.scala
@@ -667,7 +667,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
         when (decoded_addr(CSRs.tdata2)) { bp.address := wdata }
       }
     }
-    for (((pmp, next), i) <- (reg_pmp zip (reg_pmp.tail :+ reg_pmp.last)) zipWithIndex) {
+    if (reg_pmp.nonEmpty) for (((pmp, next), i) <- (reg_pmp zip (reg_pmp.tail :+ reg_pmp.last)) zipWithIndex) {
       require(xLen % pmp.cfg.getWidth == 0)
       when (decoded_addr(CSRs.pmpcfg0 + pmpCfgIndex(i)) && !pmp.locked) {
         pmp.cfg := new PMPConfig().fromBits(wdata >> ((i * pmp.cfg.getWidth) % xLen))
diff --git a/src/main/scala/rocket/PMP.scala b/src/main/scala/rocket/PMP.scala
index e6f25d9e..d75db2fc 100644
--- a/src/main/scala/rocket/PMP.scala
+++ b/src/main/scala/rocket/PMP.scala
@@ -136,7 +136,7 @@ class PMPChecker(lgMaxSize: Int)(implicit p: Parameters) extends CoreModule()(p)
     val x = Bool(OUTPUT)
   }
 
-  val default = io.prv > PRV.S
+  val default = if (io.pmp.isEmpty) true.B else io.prv > PRV.S
   val pmp0 = Wire(init = 0.U.asTypeOf(new PMP))
   pmp0.cfg.r := default
   pmp0.cfg.w := default
diff --git a/src/main/scala/rocket/Rocket.scala b/src/main/scala/rocket/Rocket.scala
index 2b729a63..51dd8316 100644
--- a/src/main/scala/rocket/Rocket.scala
+++ b/src/main/scala/rocket/Rocket.scala
@@ -18,7 +18,7 @@ case class RocketCoreParams(
   useAtomics: Boolean = true,
   useCompressed: Boolean = true,
   nBreakpoints: Int = 1,
-  nPMPs: Int = 16,
+  nPMPs: Int = 8,
   nPerfCounters: Int = 0,
   nCustomMRWCSRs: Int = 0,
   mtvecInit: Option[BigInt] = Some(BigInt(0)),