riscv/rocket-chip
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Default to 8 PMPs; support 0 PMPs

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This commit is contained in:
Andrew Waterman committed 2017-03-24 16:39:52 -07:00
1 parent 97006ab396
commit 17b1ee3037
4 files changed
+4 -4
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src/main/scala/rocket/CSR.scala
+1 -1
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@@ -667,7 +667,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
when (decoded_addr(CSRs.tdata2)) { bp.address := wdata }
}
}
for (((pmp, next), i) <- (reg_pmp zip (reg_pmp.tail :+ reg_pmp.last)) zipWithIndex) {
if (reg_pmp.nonEmpty) for (((pmp, next), i) <- (reg_pmp zip (reg_pmp.tail :+ reg_pmp.last)) zipWithIndex) {
require(xLen % pmp.cfg.getWidth == 0)
when (decoded_addr(CSRs.pmpcfg0 + pmpCfgIndex(i)) && !pmp.locked) {
pmp.cfg := new PMPConfig().fromBits(wdata >> ((i * pmp.cfg.getWidth) % xLen))