riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

changed coherence type width names to represent max sizes for all protocols

Browse Source
This commit is contained in:
Henry Cook 2012-04-04 13:57:08 -07:00
parent 6bc47a55b4
commit 17a5d26c1e
2 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
uncore/coherence.scala
View File

@ -4,7 +4,7 @@ import Chisel._
import Constants._
class TransactionInit extends Bundle {
val x_type = Bits(width = X_INIT_TYPE_BITS)
val x_type = Bits(width = X_INIT_TYPE_MAX_BITS)
val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
val address = UFix(width = PADDR_BITS - OFFSET_BITS)
}
@ -16,20 +16,20 @@ class TransactionAbort extends Bundle {
}
class ProbeRequest extends Bundle {
val p_type = Bits(width = P_REQ_TYPE_BITS)
val p_type = Bits(width = P_REQ_TYPE_MAX_BITS)
val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
val address = Bits(width = PADDR_BITS - OFFSET_BITS)
}
class ProbeReply extends Bundle {
val p_type = Bits(width = P_REP_TYPE_BITS)
val p_type = Bits(width = P_REP_TYPE_MAX_BITS)
val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
}
class ProbeReplyData extends MemData
class TransactionReply extends MemData {
val x_type = Bits(width = X_REP_TYPE_BITS)
val x_type = Bits(width = X_REP_TYPE_MAX_BITS)
val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
val require_ack = Bool()
@ -57,10 +57,10 @@ trait ThreeStateIncoherence extends CoherencePolicy {
val xactInitReadShared = UFix(0, 2)
val xactInitReadExclusive = UFix(1, 2)
val xactInitWriteUncached = UFix(3, 2)
val xactReplyReadShared = UFix(0, X_REP_TYPE_BITS)
val xactReplyReadExclusive = UFix(1, X_REP_TYPE_BITS)
val xactReplyWriteUncached = UFix(3, X_REP_TYPE_BITS)
val probeRepInvalidateAck = UFix(3, P_REP_TYPE_BITS)
val xactReplyReadShared = UFix(0, X_REP_TYPE_MAX_BITS)
val xactReplyReadExclusive = UFix(1, X_REP_TYPE_MAX_BITS)
val xactReplyWriteUncached = UFix(3, X_REP_TYPE_MAX_BITS)
val probeRepInvalidateAck = UFix(3, P_REP_TYPE_MAX_BITS)
def isHit ( cmd: Bits, state: UFix): Bool = {
val (read, write) = cpuCmdToRW(cmd)

4
uncore/uncore.scala
View File

@ -74,7 +74,7 @@ class XactTracker(ntiles: Int, id: Int) extends Component with FourStateCoherenc
val p_rep_tile_id = Bits(TILE_ID_BITS, OUTPUT)
val tile_xact_id = Bits(TILE_XACT_ID_BITS, OUTPUT)
val sharer_count = Bits(TILE_ID_BITS+1, OUTPUT)
val x_type = Bits(X_INIT_TYPE_BITS, OUTPUT)
val x_type = Bits(X_INIT_TYPE_MAX_BITS, OUTPUT)
val push_p_req = Bits(ntiles, OUTPUT)
val pop_p_rep = Bits(ntiles, OUTPUT)
val pop_p_rep_data = Bits(ntiles, OUTPUT)
@ -283,7 +283,7 @@ class CoherenceHubBroadcast(ntiles: Int) extends CoherenceHub(ntiles) with FourS
val addr_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=PADDR_BITS-OFFSET_BITS)} }
val init_tile_id_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} }
val tile_xact_id_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_XACT_ID_BITS)} }
val x_type_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=X_INIT_TYPE_BITS)} }
val x_type_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=X_INIT_TYPE_MAX_BITS)} }
val sh_count_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} }
val send_x_rep_ack_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }