riscv/rocket-chip
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Merge pull request #976 from freechipsproject/system-buffer

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SystemBus: add output buffering
This commit is contained in:
Wesley W. Terpstra 2017-08-30 23:22:13 +02:00 committed by GitHub
commit 173f185b17
2 changed files with 5 additions and 3 deletions
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6
src/main/scala/coreplex/SystemBus.scala
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@ -12,7 +12,7 @@ case class SystemBusParams(
beatBytes: Int,
blockBytes: Int,
masterBuffering: BufferParams = BufferParams.default,
slaveBuffering: BufferParams = BufferParams.flow // TODO should be BufferParams.none on BCE
slaveBuffering: BufferParams = BufferParams.default
) extends TLBusParams
case object SystemBusParams extends Field[SystemBusParams]
@ -29,12 +29,14 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
private val tile_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
private val port_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
private val pbus_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
master_splitter.node :=* tile_fixer.node
master_splitter.node :=* port_fixer.node
pbus_fixer.node :*= outwardWWNode
def toSplitSlaves: TLOutwardNode = outwardSplitNode
val toPeripheryBus: TLOutwardNode = outwardWWNode
val toPeripheryBus: TLOutwardNode = pbus_fixer.node
val toMemoryBus: TLOutwardNode = outwardNode

2
src/main/scala/devices/tilelink/Error.scala
View File

@ -97,5 +97,5 @@ trait HasSystemErrorSlave extends HasSystemBus {
private val params = p(ErrorParams)
val error = LazyModule(new TLError(params, sbus.beatBytes))
error.node := TLBuffer(BufferParams.pipe)(sbus.toSlave)
error.node := sbus.toSlave
}