From bf19440db56867e56e25ce55a2ebf6a31b6b2528 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Sat, 26 Aug 2017 02:47:04 -0700 Subject: [PATCH 1/2] SystemBus: use a full buffer on slaves --- src/main/scala/coreplex/SystemBus.scala | 2 +- src/main/scala/devices/tilelink/Error.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala index 30cd999c..b2558a2a 100644 --- a/src/main/scala/coreplex/SystemBus.scala +++ b/src/main/scala/coreplex/SystemBus.scala @@ -12,7 +12,7 @@ case class SystemBusParams( beatBytes: Int, blockBytes: Int, masterBuffering: BufferParams = BufferParams.default, - slaveBuffering: BufferParams = BufferParams.flow // TODO should be BufferParams.none on BCE + slaveBuffering: BufferParams = BufferParams.default ) extends TLBusParams case object SystemBusParams extends Field[SystemBusParams] diff --git a/src/main/scala/devices/tilelink/Error.scala b/src/main/scala/devices/tilelink/Error.scala index bc43b4ff..d054922e 100644 --- a/src/main/scala/devices/tilelink/Error.scala +++ b/src/main/scala/devices/tilelink/Error.scala @@ -97,5 +97,5 @@ trait HasSystemErrorSlave extends HasSystemBus { private val params = p(ErrorParams) val error = LazyModule(new TLError(params, sbus.beatBytes)) - error.node := TLBuffer(BufferParams.pipe)(sbus.toSlave) + error.node := sbus.toSlave } From 656609d610e412006da9abdd301e9c48664f5f19 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 30 Aug 2017 13:28:11 -0700 Subject: [PATCH 2/2] SystemBus: split FIFOFixers along bus boundaries If you have a system with a lot of periphery slaves, you wan to FIFO fix them on the periphery bus rather than paying the circuit cost at the sbus. --- src/main/scala/coreplex/SystemBus.scala | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala index b2558a2a..05fc6081 100644 --- a/src/main/scala/coreplex/SystemBus.scala +++ b/src/main/scala/coreplex/SystemBus.scala @@ -29,12 +29,14 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr private val tile_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable)) private val port_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all)) + private val pbus_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all)) master_splitter.node :=* tile_fixer.node master_splitter.node :=* port_fixer.node + pbus_fixer.node :*= outwardWWNode def toSplitSlaves: TLOutwardNode = outwardSplitNode - val toPeripheryBus: TLOutwardNode = outwardWWNode + val toPeripheryBus: TLOutwardNode = pbus_fixer.node val toMemoryBus: TLOutwardNode = outwardNode