riscv/rocket-chip
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L2 alloc cleanup

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This commit is contained in:
Henry Cook
2015-05-12 17:14:06 -07:00
parent 5fdae2cb61
commit 172c372d3e
2 changed files with 5 additions and 2 deletions
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3
uncore/src/main/scala/uncore.scala
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@ -114,6 +114,9 @@ abstract class XactTracker extends CoherenceAgentModule with HasDataBeatCounters
def addPendingBitWhenBeatHasData[T <: HasBeat](in: DecoupledIO[T]): UInt =
addPendingBitWhenBeat(in.fire() && in.bits.hasData(), in.bits)
def addPendingBitWhenBeatHasDataAndAllocs(in: DecoupledIO[AcquireFromSrc]): UInt =
addPendingBitWhenBeat(in.fire() && in.bits.hasData() && in.bits.allocate(), in.bits)
def addPendingBitWhenBeatIsGetOrAtomic(in: DecoupledIO[AcquireFromSrc]): UInt = {
val a = in.bits
val isGetOrAtomic = a.isBuiltInType() &&