riscv/rocket-chip
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reduce HTIF clock divider for now

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This commit is contained in:
Andrew Waterman 2012-05-03 04:21:11 -07:00
parent e1f9dc2c1f
commit 171c87002e
2 changed files with 6 additions and 5 deletions
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5
rocket/src/main/scala/slowio.scala
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@ -3,7 +3,7 @@ package rocket
import Chisel._ import Chisel._
import Constants._ import Constants._
class slowIO[T <: Data](divisor: Int, hold_cycles: Int)(data: => T) extends Component class slowIO[T <: Data](val divisor: Int, hold_cycles_in: Int = -1)(data: => T) extends Component
{ {
val io = new Bundle { val io = new Bundle {
val out_fast = new ioDecoupled()(data).flip val out_fast = new ioDecoupled()(data).flip
@ -15,8 +15,9 @@ class slowIO[T <: Data](divisor: Int, hold_cycles: Int)(data: => T) extends Comp
val clk_slow = Bool(OUTPUT) val clk_slow = Bool(OUTPUT)
} }
val hold_cycles = if (hold_cycles_in == -1) divisor/4 else hold_cycles_in
require((divisor & (divisor-1)) == 0) require((divisor & (divisor-1)) == 0)
require(hold_cycles < divisor/2 && hold_cycles >= 2) require(hold_cycles < divisor/2 && hold_cycles >= 1)
val cnt = Reg() { UFix(width = log2up(divisor)) } val cnt = Reg() { UFix(width = log2up(divisor)) }
cnt := cnt + UFix(1) cnt := cnt + UFix(1)

6
rocket/src/main/scala/top.scala
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@ -16,7 +16,7 @@ class ioTop(htif_width: Int) extends Bundle {
class Top extends Component class Top extends Component
{ {
val clkdiv = 32 val clkdiv = 8
val htif_width = 8 val htif_width = 8
val io = new ioTop(htif_width) val io = new ioTop(htif_width)
@ -53,7 +53,7 @@ class Top extends Component
hub.io.mem.resp.bits := Mux(io.mem_backup_en, mem_serdes.io.wide.resp.bits, io.mem.resp.bits) hub.io.mem.resp.bits := Mux(io.mem_backup_en, mem_serdes.io.wide.resp.bits, io.mem.resp.bits)
// pad out the HTIF using a divided clock // pad out the HTIF using a divided clock
val hio = (new slowIO(clkdiv, 4)) { Bits(width = htif_width) } val hio = (new slowIO(clkdiv)) { Bits(width = htif_width) }
htif.io.host.out <> hio.io.out_fast htif.io.host.out <> hio.io.out_fast
io.host.out <> hio.io.out_slow io.host.out <> hio.io.out_slow
htif.io.host.in <> hio.io.in_fast htif.io.host.in <> hio.io.in_fast
@ -61,7 +61,7 @@ class Top extends Component
io.host_clk := hio.io.clk_slow io.host_clk := hio.io.clk_slow
// pad out the backup memory link with the HTIF divided clk // pad out the backup memory link with the HTIF divided clk
val mio = (new slowIO(clkdiv, 4)) { Bits(width = MEM_BACKUP_WIDTH) } val mio = (new slowIO(clkdiv)) { Bits(width = MEM_BACKUP_WIDTH) }
mem_serdes.io.narrow.req <> mio.io.out_fast mem_serdes.io.narrow.req <> mio.io.out_fast
io.mem_backup.req <> mio.io.out_slow io.mem_backup.req <> mio.io.out_slow
mem_serdes.io.narrow.resp.valid := mio.io.in_fast.valid mem_serdes.io.narrow.resp.valid := mio.io.in_fast.valid