riscv/rocket-chip
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fixes after merge

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This commit is contained in:
Henry Cook
2013-03-25 19:09:08 -07:00
parent 95f0a688e9
commit 16113a96ba
2 changed files with 3 additions and 3 deletions
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4
rocket/src/main/scala/tile.scala
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@ -55,13 +55,13 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Compon
io.tilelink.release.bits := dcache.io.mem.release.bits
io.tilelink.release.bits.payload.client_xact_id := Cat(dcache.io.mem.release.bits.payload.client_xact_id, UFix(dcachePortId, log2Up(memPorts))) // Mimic client id extension done by UncachedTileLinkIOArbiter for Acquires from either client)
val ioSubBundles = io.tilelink.getClass.getMethods.filter( x =>
/*val ioSubBundles = io.tilelink.getClass.getMethods.filter( x =>
classOf[ClientSourcedIO[Data]].isAssignableFrom(x.getReturnType)).map{ m =>
m.invoke(io.tilelink).asInstanceOf[ClientSourcedIO[LogicalNetworkIO[Data]]] }
ioSubBundles.foreach{ m =>
m.bits.header.dst := UFix(0)
m.bits.header.src := UFix(0)
}
}*/
if (conf.vec) {
val vicache = new Frontend()(ICacheConfig(128, 1, conf.co), lnConf) // 128 sets x 1 ways (8KB)