riscv/rocket-chip
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Remove HTIF CPU port

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This commit is contained in:
Andrew Waterman 2016-05-03 13:55:59 -07:00
parent 487d0b356e
commit 15f4af19cf
5 changed files with 9 additions and 18 deletions
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2
chisel3

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Subproject commit 6183533596a1706c65cb20d07a9d42eadac32df2 Subproject commit 0ad47ff929aa084d6aff4d378b32968ef19b97c7

2
firrtl

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Subproject commit 54184c2a08aea4c8682d2fe899718c369e00a240 Subproject commit 592ee2fbc53219a39bf2da505fd761b412bf5cff

2
groundtest

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Subproject commit ed6b53a337af917f48fe6a10a3a1097bc542fe55 Subproject commit 60121c48931843bcfecd1c4c2040c4f66a9e9e68

2
rocket

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Subproject commit 679c9148da9cfdfff292958ebc2cb451f5787b6e Subproject commit 9f853450deb5996251e88dfa75f715593ca2878a

19
src/main/scala/RocketChip.scala
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@ -123,16 +123,11 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
// Build an Uncore and a set of Tiles // Build an Uncore and a set of Tiles
val innerTLParams = p.alterPartial({case TLId => "L1toL2" }) val innerTLParams = p.alterPartial({case TLId => "L1toL2" })
val uncore = Module(new Uncore()(innerTLParams)) val uncore = Module(new Uncore()(innerTLParams))
val tileList = uncore.io.htif zip p(BuildTiles) map { case(hl, bt) => bt(hl.reset, p) } val tileList = uncore.io.prci zip p(BuildTiles) map { case(prci, tile) => tile(prci.reset, p) }
// Connect each tile to the HTIF // Connect each tile to the HTIF
for (((hl, prci), tile) <- uncore.io.htif zip uncore.io.prci zip tileList) { for ((prci, tile) <- uncore.io.prci zip tileList) {
tile.io.prci <> prci tile.io.prci <> prci
// TODO remove HTIF
tile.io.host.id := prci.id
tile.io.host.reset := prci.reset
tile.io.host.csr.req <> Queue(hl.csr.req)
hl.csr.resp <> Queue(tile.io.host.csr.resp)
} }
// Connect the uncore to the tile memory ports, HostIO and MemIO // Connect the uncore to the tile memory ports, HostIO and MemIO
@ -162,7 +157,6 @@ class Uncore(implicit val p: Parameters) extends Module
val mem = Vec(nMemChannels, new NastiIO) val mem = Vec(nMemChannels, new NastiIO)
val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip
val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip
val htif = Vec(nTiles, new HtifIO).flip
val prci = Vec(nTiles, new PRCITileIO).asOutput val prci = Vec(nTiles, new PRCITileIO).asOutput
val mmio = new NastiIO val mmio = new NastiIO
} }
@ -174,12 +168,6 @@ class Uncore(implicit val p: Parameters) extends Module
outmemsys.io.tiles_uncached <> io.tiles_uncached outmemsys.io.tiles_uncached <> io.tiles_uncached
outmemsys.io.tiles_cached <> io.tiles_cached outmemsys.io.tiles_cached <> io.tiles_cached
for (i <- 0 until nTiles) {
io.htif(i).reset := htif.io.cpu(i).reset
io.htif(i).id := htif.io.cpu(i).id
io.htif(i).csr <> htif.io.cpu(i).csr
}
val addrMap = p(GlobalAddrMap) val addrMap = p(GlobalAddrMap)
val addrHashMap = p(GlobalAddrHashMap) val addrHashMap = p(GlobalAddrHashMap)
val scrFile = Module(new SCRFile("UNCORE_SCR", 0)) val scrFile = Module(new SCRFile("UNCORE_SCR", 0))
@ -196,6 +184,9 @@ class Uncore(implicit val p: Parameters) extends Module
io.host <> htif.io.host io.host <> htif.io.host
} }
// Tie off HTIF CSR ports
htif.io.cpu.foreach { _.csr.resp.valid := Bool(false) }
def buildMMIONetwork(implicit p: Parameters) = { def buildMMIONetwork(implicit p: Parameters) = {
val (ioBase, ioAddrMap) = addrHashMap.subMap("io") val (ioBase, ioAddrMap) = addrHashMap.subMap("io")
val ioAddrHashMap = new AddrHashMap(ioAddrMap, ioBase) val ioAddrHashMap = new AddrHashMap(ioAddrMap, ioBase)