riscv/rocket-chip
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RegFieldDesc: change how reserved is indicated

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This commit is contained in:
Megan Wachs 2018-03-09 17:38:23 -08:00
parent d889a0ca16
commit 15e058e3da
3 changed files with 10 additions and 10 deletions
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6
src/main/scala/devices/tilelink/Plic.scala
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@ -173,13 +173,13 @@ class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends
reset=if (nPriorities > 0) None else Some(1), reset=if (nPriorities > 0) None else Some(1),
wrType=Some(RegFieldWrType.MODIFY)) wrType=Some(RegFieldWrType.MODIFY))
} else { } else {
RegFieldDescReserved() RegFieldDesc.reserved()
} }
def pendingRegDesc(i: Int) = if (i > 0) { def pendingRegDesc(i: Int) = if (i > 0) {
RegFieldDesc(s"pending_$i", s"Set to 1 if interrupt source $i is pending, regardless of its enable or priority setting.", RegFieldDesc(s"pending_$i", s"Set to 1 if interrupt source $i is pending, regardless of its enable or priority setting.",
volatile = true) volatile = true)
} else { } else {
RegFieldDescReserved() RegFieldDesc.reserved()
} }
def priorityRegField(x: UInt, i: Int) = if (nPriorities > 0) RegField(32, x, priorityRegDesc(i)) else RegField.r(32, x, priorityRegDesc(i)) def priorityRegField(x: UInt, i: Int) = if (nPriorities > 0) RegField(32, x, priorityRegDesc(i)) else RegField.r(32, x, priorityRegDesc(i))
@ -195,7 +195,7 @@ class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends
e.zipWithIndex.map{case (b, j) => if (j > 0) { e.zipWithIndex.map{case (b, j) => if (j > 0) {
RegField(1, b, RegFieldDesc(s"enable_${i}_${j}", s"Enable interrupt for source $j for target $i.", reset=None)) RegField(1, b, RegFieldDesc(s"enable_${i}_${j}", s"Enable interrupt for source $j for target $i.", reset=None))
} else { } else {
RegField(1, b, RegFieldDescReserved()) RegField(1, b, RegFieldDesc.reserved())
}}) }})
} }

6
src/main/scala/regmapper/RegField.scala
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@ -46,8 +46,8 @@ case class RegFieldDesc (
){ ){
} }
object RegFieldDescReserved { object RegFieldDesc {
def apply(): RegFieldDesc = RegFieldDesc("reserved", "", access=RegFieldAccessType.R, reset=Some(0)) def reserved() RegFieldDesc = RegFieldDesc("reserved", "", access=RegFieldAccessType.R, reset=Some(0))
} }
// Our descriptions are in terms of RegFields only, which is somewhat // Our descriptions are in terms of RegFields only, which is somewhat
@ -145,7 +145,7 @@ object RegField
// Byte address => sequence of bitfields, lowest index => lowest address // Byte address => sequence of bitfields, lowest index => lowest address
type Map = (Int, Seq[RegField]) type Map = (Int, Seq[RegField])
def apply(n: Int) : RegField = apply(n, (), (), Some(RegFieldDescReserved())) def apply(n: Int) : RegField = apply(n, (), (), Some(RegFieldDesc.reserved()))
def apply(n: Int, r: RegReadFn, w: RegWriteFn) : RegField = apply(n, r, w, None) def apply(n: Int, r: RegReadFn, w: RegWriteFn) : RegField = apply(n, r, w, None)
def apply(n: Int, r: RegReadFn, w: RegWriteFn, desc: RegFieldDesc) : RegField = apply(n, r, w, Some(desc)) def apply(n: Int, r: RegReadFn, w: RegWriteFn, desc: RegFieldDesc) : RegField = apply(n, r, w, Some(desc))

8
src/main/scala/rocket/BusErrorUnit.scala
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@ -63,22 +63,22 @@ class BusErrorUnit[T <: BusErrors](t: => T, params: BusErrorUnitParams)(implicit
val enable = Reg(init = Vec(sources.map(_.nonEmpty.B))) val enable = Reg(init = Vec(sources.map(_.nonEmpty.B)))
val enable_desc = sources.zipWithIndex.map { case (s, i) => val enable_desc = sources.zipWithIndex.map { case (s, i) =>
if (s.nonEmpty) RegFieldDesc(s"enable_$i", "", reset=Some(1)) if (s.nonEmpty) RegFieldDesc(s"enable_$i", "", reset=Some(1))
else RegFieldDescReserved()} else RegFieldDesc.reserved()}
val global_interrupt = Reg(init = Vec.fill(sources.size)(false.B)) val global_interrupt = Reg(init = Vec.fill(sources.size)(false.B))
val global_interrupt_desc = sources.zipWithIndex.map { case (s, i) => val global_interrupt_desc = sources.zipWithIndex.map { case (s, i) =>
if (s.nonEmpty) RegFieldDesc(s"plic_interrupt_$i", "", reset=Some(0)) if (s.nonEmpty) RegFieldDesc(s"plic_interrupt_$i", "", reset=Some(0))
else RegFieldDescReserved()} else RegFieldDesc.reserved()}
val accrued = Reg(init = Vec.fill(sources.size)(false.B)) val accrued = Reg(init = Vec.fill(sources.size)(false.B))
val accrued_desc = sources.zipWithIndex.map { case (s, i) => val accrued_desc = sources.zipWithIndex.map { case (s, i) =>
if (s.nonEmpty) RegFieldDesc(s"accrued_$i", "", reset=Some(0), volatile = true) if (s.nonEmpty) RegFieldDesc(s"accrued_$i", "", reset=Some(0), volatile = true)
else RegFieldDescReserved()} else RegFieldDesc.reserved()}
val local_interrupt = Reg(init = Vec.fill(sources.size)(false.B)) val local_interrupt = Reg(init = Vec.fill(sources.size)(false.B))
val local_interrupt_desc = sources.zipWithIndex.map { case (s, i) => val local_interrupt_desc = sources.zipWithIndex.map { case (s, i) =>
if (s.nonEmpty) RegFieldDesc(s"local_interrupt_$i", "", reset=Some(0)) if (s.nonEmpty) RegFieldDesc(s"local_interrupt_$i", "", reset=Some(0))
else RegFieldDescReserved()} else RegFieldDesc.reserved()}
for ((((s, en), acc), i) <- (sources zip enable zip accrued).zipWithIndex; if s.nonEmpty) { for ((((s, en), acc), i) <- (sources zip enable zip accrued).zipWithIndex; if s.nonEmpty) {
when (s.get.valid) { when (s.get.valid) {