227 lines
9.9 KiB
Scala
227 lines
9.9 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.regmapper
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import Chisel._
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import chisel3.util.{ReadyValidIO}
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import freechips.rocketchip.util.{SimpleRegIO}
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// This information is not used internally by the regmap(...) function.
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// However, the author of a RegField may be the best person to provide this
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// information which is likely to be needed by downstream SW and Documentation
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// tools.
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object RegFieldAccessType extends scala.Enumeration {
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type RegFieldAccessType = Value
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val R, W, RW = Value
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}
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import RegFieldAccessType._
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object RegFieldWrType extends scala.Enumeration {
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type RegFieldWrType = Value
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val ONE_TO_CLEAR, ONE_TO_SET, ONE_TO_TOGGLE, ZERO_TO_CLEAR,
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ZERO_TO_SET, ZERO_TO_TOGGLE, CLEAR, SET, MODIFY = Value
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}
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import RegFieldWrType._
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object RegFieldRdAction extends scala.Enumeration {
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type RegFieldRdAction = Value
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val CLEAR, SET, MODIFY = Value
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}
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import RegFieldRdAction._
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case class RegFieldDesc (
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name: String,
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desc: String,
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group: Option[String] = None,
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groupDesc: Option[String] = None,
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access: RegFieldAccessType = RegFieldAccessType.RW,
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wrType: Option[RegFieldWrType] = None,
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rdAction: Option[RegFieldRdAction] = None,
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volatile: Boolean = false,
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// TODO: testable?
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reset: Option[BigInt] = None,
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enumerations: Map[BigInt, (String, String)] = Map()
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){
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}
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object RegFieldDesc {
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def reserved() RegFieldDesc = RegFieldDesc("reserved", "", access=RegFieldAccessType.R, reset=Some(0))
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}
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// Our descriptions are in terms of RegFields only, which is somewhat
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// unusual for developers who are used to things being defined as bitfields
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// within registers. The "Group" allows a string & (optional) description
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// to be added which describes the conceptual "Group" the RegField belongs to.
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// This can be used by downstream flows as they see fit to present the information.
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object RegFieldGroup {
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def apply (name: String, desc: Option[String], regs: Seq[RegField], descFirstOnly: Boolean = true): Seq[RegField] = {
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regs.zipWithIndex.map {case (r, i) =>
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val gDesc = if ((i > 0) & descFirstOnly) None else desc
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r.desc.map { d =>
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r.copy(desc = Some(d.copy(group = Some(name), groupDesc = gDesc)) )
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}.getOrElse(r)
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}
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}
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}
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case class RegReadFn private(combinational: Boolean, fn: (Bool, Bool) => (Bool, Bool, UInt))
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object RegReadFn
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{
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// (ivalid: Bool, oready: Bool) => (iready: Bool, ovalid: Bool, data: UInt)
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// iready may combinationally depend on oready
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// all other combinational dependencies forbidden (e.g. ovalid <= ivalid)
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// effects must become visible on the cycle after ovalid && oready
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// data is only inspected when ovalid && oready
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implicit def apply(x: (Bool, Bool) => (Bool, Bool, UInt)) =
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new RegReadFn(false, x)
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implicit def apply(x: RegisterReadIO[UInt]): RegReadFn =
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RegReadFn((ivalid, oready) => {
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x.request.valid := ivalid
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x.response.ready := oready
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(x.request.ready, x.response.valid, x.response.bits)
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})
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// (ready: Bool) => (valid: Bool, data: UInt)
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// valid must not combinationally depend on ready
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// effects must become visible on the cycle after valid && ready
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implicit def apply(x: Bool => (Bool, UInt)) =
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new RegReadFn(true, { case (_, oready) =>
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val (ovalid, data) = x(oready)
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(Bool(true), ovalid, data)
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})
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// read from a ReadyValidIO (only safe if there is a consistent source of data)
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implicit def apply(x: ReadyValidIO[UInt]):RegReadFn = RegReadFn(ready => { x.ready := ready; (x.valid, x.bits) })
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// read from a register
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implicit def apply(x: UInt):RegReadFn = RegReadFn(ready => (Bool(true), x))
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// noop
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implicit def apply(x: Unit):RegReadFn = RegReadFn(UInt(0))
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}
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case class RegWriteFn private(combinational: Boolean, fn: (Bool, Bool, UInt) => (Bool, Bool))
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object RegWriteFn
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{
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// (ivalid: Bool, oready: Bool, data: UInt) => (iready: Bool, ovalid: Bool)
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// iready may combinationally depend on both oready and data
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// all other combinational dependencies forbidden (e.g. ovalid <= ivalid)
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// effects must become visible on the cycle after ovalid && oready
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// data should only be used for an effect when ivalid && iready
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implicit def apply(x: (Bool, Bool, UInt) => (Bool, Bool)) =
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new RegWriteFn(false, x)
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implicit def apply(x: RegisterWriteIO[UInt]): RegWriteFn =
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RegWriteFn((ivalid, oready, data) => {
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x.request.valid := ivalid
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x.request.bits := data
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x.response.ready := oready
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(x.request.ready, x.response.valid)
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})
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// (valid: Bool, data: UInt) => (ready: Bool)
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// ready may combinationally depend on data (but not valid)
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// effects must become visible on the cycle after valid && ready
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implicit def apply(x: (Bool, UInt) => Bool) =
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// combinational => data valid on oready
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new RegWriteFn(true, { case (_, oready, data) =>
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(Bool(true), x(oready, data))
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})
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// write to a DecoupledIO (only safe if there is a consistent sink draining data)
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// NOTE: this is not an IrrevocableIO (even on TL2) because other fields could cause a lowered valid
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implicit def apply(x: DecoupledIO[UInt]): RegWriteFn = RegWriteFn((valid, data) => { x.valid := valid; x.bits := data; x.ready })
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// updates a register (or adds a mux to a wire)
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implicit def apply(x: UInt): RegWriteFn = RegWriteFn((valid, data) => { when (valid) { x := data }; Bool(true) })
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// noop
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implicit def apply(x: Unit): RegWriteFn = RegWriteFn((valid, data) => { Bool(true) })
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}
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case class RegField(width: Int, read: RegReadFn, write: RegWriteFn, desc: Option[RegFieldDesc])
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{
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require (width > 0, s"RegField width must be > 0, not $width")
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def pipelined = !read.combinational || !write.combinational
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def readOnly = this.copy(write = (), desc = this.desc.map(_.copy(access = RegFieldAccessType.R)))
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}
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object RegField
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{
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// Byte address => sequence of bitfields, lowest index => lowest address
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type Map = (Int, Seq[RegField])
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def apply(n: Int) : RegField = apply(n, (), (), Some(RegFieldDesc.reserved()))
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def apply(n: Int, r: RegReadFn, w: RegWriteFn) : RegField = apply(n, r, w, None)
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def apply(n: Int, r: RegReadFn, w: RegWriteFn, desc: RegFieldDesc) : RegField = apply(n, r, w, Some(desc))
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def apply(n: Int, rw: UInt) : RegField = apply(n, rw, rw, None)
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def apply(n: Int, rw: UInt, desc: RegFieldDesc) : RegField = apply(n, rw, rw, Some(desc))
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def r(n: Int, r: RegReadFn) : RegField = apply(n, r, (), None)
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def r(n: Int, r: RegReadFn, desc: RegFieldDesc) : RegField = apply(n, r, (), Some(desc.copy(access = RegFieldAccessType.R)))
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def w(n: Int, w: RegWriteFn) : RegField = apply(n, (), w, None)
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def w(n: Int, w: RegWriteFn, desc: RegFieldDesc) : RegField = apply(n, (), w, Some(desc.copy(access = RegFieldAccessType.W)))
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// This RegField allows 'set' to set bits in 'reg'.
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// and to clear bits when the bus writes bits of value 1.
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// Setting takes priority over clearing.
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def w1ToClear(n: Int, reg: UInt, set: UInt, desc: Option[RegFieldDesc] = None): RegField =
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RegField(n, reg, RegWriteFn((valid, data) => { reg := ~(~reg | Mux(valid, data, UInt(0))) | set; Bool(true) }),
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desc.map{_.copy(access = RegFieldAccessType.RW, wrType=Some(RegFieldWrType.ONE_TO_CLEAR), volatile = true)})
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// This RegField wraps an explicit register
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// (e.g. Black-Boxed Register) to create a R/W register.
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def rwReg(n: Int, bb: SimpleRegIO, desc: Option[RegFieldDesc] = None) : RegField =
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RegField(n, bb.q, RegWriteFn((valid, data) => {
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bb.en := valid
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bb.d := data
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Bool(true)
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}), desc)
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// Create byte-sized read-write RegFields out of a large UInt register.
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// It is updated when any of the (implemented) bytes are written, the non-written
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// bytes are just copied over from their current value.
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// Because the RegField are all byte-sized, this is also suitable when a register is larger
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// than the intended bus width of the device (atomic updates are impossible).
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def bytes(reg: UInt, numBytes: Int, desc: Option[RegFieldDesc]): Seq[RegField] = {
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require(reg.getWidth * 8 >= numBytes, "Can't break a ${reg.getWidth}-bit-wide register into only ${numBytes} bytes.")
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val numFullBytes = reg.getWidth/8
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val numPartialBytes = if ((reg.getWidth % 8) > 0) 1 else 0
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val numPadBytes = numBytes - numFullBytes - numPartialBytes
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val pad = reg | UInt(0, width = 8*numBytes)
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val oldBytes = Vec.tabulate(numBytes) { i => pad(8*(i+1)-1, 8*i) }
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val newBytes = Wire(init = oldBytes)
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val valids = Wire(init = Vec.fill(numBytes) { Bool(false) })
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when (valids.reduce(_ || _)) { reg := newBytes.asUInt }
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def wrFn(i: Int): RegWriteFn = RegWriteFn((valid, data) => {
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valids(i) := valid
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when (valid) {newBytes(i) := data}
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Bool(true)
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})
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val fullBytes = Seq.tabulate(numFullBytes) { i =>
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val newDesc = desc.map {d => d.copy(name = d.name + s"_$i")}
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RegField(8, oldBytes(i), wrFn(i), newDesc)}
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val partialBytes = if (numPartialBytes > 0) {
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val newDesc = desc.map {d => d.copy(name = d.name + s"_$numFullBytes")}
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Seq(RegField(reg.getWidth % 8, oldBytes(numFullBytes), wrFn(numFullBytes), newDesc),
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RegField(8 - (reg.getWidth % 8)))
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} else Nil
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val padBytes = Seq.fill(numPadBytes){RegField(8)}
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fullBytes ++ partialBytes ++ padBytes
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}
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def bytes(reg: UInt, desc: Option[RegFieldDesc]): Seq[RegField] = {
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val width = reg.getWidth
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require (width % 8 == 0, s"RegField.bytes must be called on byte-sized reg, not ${width} bits")
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bytes(reg, width/8, desc)
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}
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def bytes(reg: UInt, numBytes: Int): Seq[RegField] = bytes(reg, numBytes, None)
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def bytes(reg: UInt): Seq[RegField] = bytes(reg, None)
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}
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trait HasRegMap
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{
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def regmap(mapping: RegField.Map*): Unit
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val interrupts: Vec[Bool]
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}
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// See Example.scala for an example of how to use regmap
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