riscv/rocket-chip
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tile: intSinkNode belongs in HasExternalInterrupts

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Henry Cook committed 2018-01-08 19:38:10 -08:00
1 parent 11e5b620f8
commit 15c54b1c5a
2 files changed
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src/main/scala/tile/BaseTile.scala
-1
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@@ -135,7 +135,6 @@ abstract class BaseTile(tileParams: TileParams, val crossing: CoreplexClockCross
protected val tlMasterXbar = LazyModule(new TLXbar) protected val tlMasterXbar = LazyModule(new TLXbar)
protected val tlSlaveXbar = LazyModule(new TLXbar) protected val tlSlaveXbar = LazyModule(new TLXbar)
protected val intXbar = LazyModule(new IntXbar) protected val intXbar = LazyModule(new IntXbar)
protected val intSinkNode = IntSinkNode(IntSinkPortSimple())
def connectTLSlave(node: TLNode, bytes: Int) { def connectTLSlave(node: TLNode, bytes: Int) {
DisableMonitors { implicit p => DisableMonitors { implicit p =>
src/main/scala/tile/Interrupts.scala
+1
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@@ -22,6 +22,7 @@ class TileInterrupts(implicit p: Parameters) extends CoreBundle()(p) {
trait HasExternalInterrupts { this: BaseTile => trait HasExternalInterrupts { this: BaseTile =>
val intInwardNode = intXbar.intnode val intInwardNode = intXbar.intnode
protected val intSinkNode = IntSinkNode(IntSinkPortSimple())
intSinkNode := intXbar.intnode intSinkNode := intXbar.intnode
val intcDevice = new Device { val intcDevice = new Device {