diff --git a/src/main/scala/tile/BaseTile.scala b/src/main/scala/tile/BaseTile.scala
index c8c669a2..40f2b8da 100644
--- a/src/main/scala/tile/BaseTile.scala
+++ b/src/main/scala/tile/BaseTile.scala
@@ -135,7 +135,6 @@ abstract class BaseTile(tileParams: TileParams, val crossing: CoreplexClockCross
   protected val tlMasterXbar = LazyModule(new TLXbar)
   protected val tlSlaveXbar = LazyModule(new TLXbar)
   protected val intXbar = LazyModule(new IntXbar)
-  protected val intSinkNode = IntSinkNode(IntSinkPortSimple())
 
   def connectTLSlave(node: TLNode, bytes: Int) {
     DisableMonitors { implicit p =>
diff --git a/src/main/scala/tile/Interrupts.scala b/src/main/scala/tile/Interrupts.scala
index 13c5d64e..6e81f109 100644
--- a/src/main/scala/tile/Interrupts.scala
+++ b/src/main/scala/tile/Interrupts.scala
@@ -22,6 +22,7 @@ class TileInterrupts(implicit p: Parameters) extends CoreBundle()(p) {
 trait HasExternalInterrupts { this: BaseTile =>
 
   val intInwardNode = intXbar.intnode
+  protected val intSinkNode = IntSinkNode(IntSinkPortSimple())
   intSinkNode := intXbar.intnode
 
   val intcDevice = new Device {