riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Fixed cache params. Asm and bmark tests pass.

Browse Source
This commit is contained in:
Henry Cook
2014-08-12 15:00:54 -07:00
parent 910c886837
commit 1563c1bb36
2 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/RocketChip.scala
View File

@ -310,7 +310,7 @@ class Top extends Module {
//val vic = ICacheConfig(sets = 128, assoc = 1, tl = tl, as = as, btb = BTBConfig(as, 8)) //val vic = ICacheConfig(sets = 128, assoc = 1, tl = tl, as = as, btb = BTBConfig(as, 8))
//val hc = hwacha.HwachaConfiguration(as, vic, dc, 8, 256, ndtlb = 8, nptlb = 2) //val hc = hwacha.HwachaConfiguration(as, vic, dc, 8, 256, ndtlb = 8, nptlb = 2)
val nTiles = params(NTiles) val nTiles = params[Int]("NTILES")
val io = new VLSITopIO val io = new VLSITopIO
val tl: PartialFunction[Any,Any] = params(TileLinkL1Params) //TODO PARAMS can't lookup in map() below? val tl: PartialFunction[Any,Any] = params(TileLinkL1Params) //TODO PARAMS can't lookup in map() below?

2
uncore

Submodule uncore updated: 041a1ec127...37fdf25582