From 1563c1bb36eeba69fb3ae10e03aff3f2da1cbef3 Mon Sep 17 00:00:00 2001
From: Henry Cook <hcook@eecs.berkeley.edu>
Date: Tue, 12 Aug 2014 15:00:54 -0700
Subject: [PATCH] Fixed cache params. Asm and bmark tests pass.

---
 src/main/scala/RocketChip.scala | 2 +-
 uncore                          | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index c78358f7..2ae088ab 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -310,7 +310,7 @@ class Top extends Module {
   //val vic = ICacheConfig(sets = 128, assoc = 1, tl = tl, as = as, btb = BTBConfig(as, 8))
   //val hc = hwacha.HwachaConfiguration(as, vic, dc, 8, 256, ndtlb = 8, nptlb = 2)
 
-  val nTiles = params(NTiles)
+  val nTiles = params[Int]("NTILES")
   val io = new VLSITopIO
 
   val tl: PartialFunction[Any,Any] = params(TileLinkL1Params) //TODO PARAMS can't lookup in map() below?
diff --git a/uncore b/uncore
index 041a1ec1..37fdf255 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit 041a1ec127634413314bc9d6241fd12860950e70
+Subproject commit 37fdf25582b9c0ef48dceecb76416c955f0bc81e