riscv/rocket-chip
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make sure ClientTileLinkEnqueuer uses the correct parameters

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Howard Mao 2015-11-10 16:09:19 -08:00
parent 51f128ec74
commit 149480411e
1 changed files with 1 additions and 1 deletions
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src/main/scala/RocketChip.scala
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@ -244,7 +244,7 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams)) val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams))
val narrow = Module(new TileLinkIONarrower("L2toMC", "Outermost")) val narrow = Module(new TileLinkIONarrower("L2toMC", "Outermost"))
val conv = Module(new NastiIOTileLinkIOConverter()(outermostTLParams)) val conv = Module(new NastiIOTileLinkIOConverter()(outermostTLParams))
unwrap.io.in <> ClientTileLinkEnqueuer(bank.outerTL, backendBuffering) unwrap.io.in <> ClientTileLinkEnqueuer(bank.outerTL, backendBuffering)(outerTLParams)
narrow.io.in <> unwrap.io.out narrow.io.in <> unwrap.io.out
conv.io.tl <> narrow.io.out conv.io.tl <> narrow.io.out
TopUtils.connectNasti(interconnect.io.masters(i), conv.io.nasti) TopUtils.connectNasti(interconnect.io.masters(i), conv.io.nasti)