diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index cdd43db9..7a5476f9 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -244,7 +244,7 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
     val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams))
     val narrow = Module(new TileLinkIONarrower("L2toMC", "Outermost"))
     val conv = Module(new NastiIOTileLinkIOConverter()(outermostTLParams))
-    unwrap.io.in <> ClientTileLinkEnqueuer(bank.outerTL, backendBuffering)
+    unwrap.io.in <> ClientTileLinkEnqueuer(bank.outerTL, backendBuffering)(outerTLParams)
     narrow.io.in <> unwrap.io.out
     conv.io.tl <> narrow.io.out
     TopUtils.connectNasti(interconnect.io.masters(i), conv.io.nasti)