add probe replies to HTIF
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b0f798962c
commit
1492457df5
@ -21,7 +21,7 @@ class ioHTIF extends Bundle
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val pcr_rdata = Bits(64, OUTPUT)
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}
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class rocketHTIF(w: Int, ncores: Int) extends Component
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class rocketHTIF(w: Int, ncores: Int) extends Component with FourStateCoherence
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{
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val io = new Bundle {
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val host = new ioHost(w)
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@ -160,6 +160,13 @@ class rocketHTIF(w: Int, ncores: Int) extends Component
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io.mem.xact_finish.valid := (state === state_mem_finish) && mem_needs_ack
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io.mem.xact_finish.bits.global_xact_id := mem_gxid
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val probe_q = (new queue(1, pipe=true)) { new TransactionReply }
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probe_q.io.enq.valid := io.mem.probe_req.valid
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io.mem.probe_req.ready := probe_q.io.enq.ready
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probe_q.io.enq.bits := newProbeReply(io.mem.probe_req.bits, newStateOnFlush())
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io.mem.probe_rep <> probe_q.io.deq
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io.mem.probe_rep_data.valid := Bool(false)
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pcr_done := Bool(false)
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val pcr_mux = (new Mux1H(ncores)) { Bits(width = 64) }
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for (i <- 0 until ncores) {
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@ -492,7 +492,7 @@ class ProbeUnit extends Component with FourStateCoherence {
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val meta_req = (new ioDecoupled) { new MetaArrayArrayReq }
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val mshr_req = (new ioDecoupled) { Bool() }
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val wb_req = (new ioDecoupled) { new WritebackReq }
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val hit_way_oh = Bits(NWAYS, INPUT)
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val tag_match_way_oh = Bits(NWAYS, INPUT)
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val line_state = UFix(2, INPUT)
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val address = Bits(PADDR_BITS-OFFSET_BITS, OUTPUT)
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}
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@ -513,7 +513,7 @@ class ProbeUnit extends Component with FourStateCoherence {
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state := Mux(way_oh.orR && needsWriteback(line_state), s_writeback_req, s_invalid)
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}
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when (state === s_meta_resp) {
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way_oh := io.hit_way_oh
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way_oh := io.tag_match_way_oh
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line_state := io.line_state
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state := Mux(!io.mshr_req.ready, s_meta_req, s_probe_rep)
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}
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@ -891,7 +891,7 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
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prober.io.meta_req <> meta_arb.io.in(2)
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prober.io.mshr_req <> mshr.io.probe
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prober.io.wb_req <> wb.io.probe
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prober.io.hit_way_oh := hit_way_oh
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prober.io.tag_match_way_oh := tag_match_way_oh
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prober.io.line_state := meta_resp_mux.state
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// replacement policy
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