riscv/rocket-chip
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Remove extraneous signal

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This commit is contained in:
Andrew Waterman 2017-10-09 18:33:50 -07:00
parent f3825270c1
commit 1474ab438d
1 changed files with 0 additions and 1 deletions
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src/main/scala/rocket/TLB.scala
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@ -28,7 +28,6 @@ class SFenceReq(implicit p: Parameters) extends CoreBundle()(p) {
class TLBReq(lgMaxSize: Int)(implicit p: Parameters) extends CoreBundle()(p) {
val vaddr = UInt(width = vaddrBitsExtended)
val passthrough = Bool()
val instruction = Bool()
val sfence = Valid(new SFenceReq)
val size = UInt(width = log2Ceil(lgMaxSize + 1))
val cmd = Bits(width = M_SZ)