From 1474ab438d185be4f6357309246a7209271da2b2 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 9 Oct 2017 18:33:50 -0700 Subject: [PATCH] Remove extraneous signal --- src/main/scala/rocket/TLB.scala | 1 - 1 file changed, 1 deletion(-) diff --git a/src/main/scala/rocket/TLB.scala b/src/main/scala/rocket/TLB.scala index 973c631e..b757e472 100644 --- a/src/main/scala/rocket/TLB.scala +++ b/src/main/scala/rocket/TLB.scala @@ -28,7 +28,6 @@ class SFenceReq(implicit p: Parameters) extends CoreBundle()(p) { class TLBReq(lgMaxSize: Int)(implicit p: Parameters) extends CoreBundle()(p) { val vaddr = UInt(width = vaddrBitsExtended) val passthrough = Bool() - val instruction = Bool() val sfence = Valid(new SFenceReq) val size = UInt(width = log2Ceil(lgMaxSize + 1)) val cmd = Bits(width = M_SZ)