riscv/rocket-chip
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fix assert

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Henry Cook
2015-03-17 05:40:05 -07:00
parent 0e51fef200
commit 1471d9debc
1 changed files with 1 additions and 0 deletions
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uncore/src/main/scala/cache.scala
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@@ -754,6 +754,7 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
//TODO: Assumes in-order network //TODO: Assumes in-order network
assert(!(state === s_idle && io.inner.acquire.fire() && assert(!(state === s_idle && io.inner.acquire.fire() &&
!io.iacq().isSubBlockType() &&
io.iacq().addr_beat != UInt(0)), io.iacq().addr_beat != UInt(0)),
"AcquireTracker initialized with a tail data beat.") "AcquireTracker initialized with a tail data beat.")