riscv/rocket-chip
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fix Chisel3 compat warnings in ICache and FPU

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This commit is contained in:
Howard Mao
2016-01-12 12:42:57 -08:00
parent 05b359d357
commit 13ce91e453
3 changed files with 8 additions and 9 deletions
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rocket/src/main/scala/frontend.scala
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@ -100,7 +100,6 @@ class Frontend(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePa
icache.io.req.bits.kill := io.cpu.req.valid ||
tlb.io.resp.miss || tlb.io.resp.xcpt_if ||
icmiss || io.ptw.invalidate
icache.io.resp.ready := !stall && !s1_same_block
io.cpu.resp.valid := s2_valid && (s2_xcpt_if || s2_resp_valid)
io.cpu.resp.bits.pc := s2_pc