From 13ce91e45346380bfb84d3daafc8f7db2cb37cd3 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Tue, 12 Jan 2016 12:42:57 -0800
Subject: [PATCH] fix Chisel3 compat warnings in ICache and FPU

---
 rocket/src/main/scala/fpu.scala      |  2 +-
 rocket/src/main/scala/frontend.scala |  1 -
 rocket/src/main/scala/icache.scala   | 14 +++++++-------
 3 files changed, 8 insertions(+), 9 deletions(-)

diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala
index 4a9a5e1a..9be609a6 100644
--- a/rocket/src/main/scala/fpu.scala
+++ b/rocket/src/main/scala/fpu.scala
@@ -452,7 +452,7 @@ class FPU(implicit p: Parameters) extends CoreModule()(p) {
   val fp_decoder = Module(new FPUDecoder)
   fp_decoder.io.inst := io.inst
 
-  val cp_ctrl = new FPUCtrlSigs
+  val cp_ctrl = Wire(new FPUCtrlSigs)
   cp_ctrl <> io.cp_req.bits
   io.cp_resp.valid := Bool(false)
   io.cp_resp.bits.data := UInt(0)
diff --git a/rocket/src/main/scala/frontend.scala b/rocket/src/main/scala/frontend.scala
index fd45d299..717cac7a 100644
--- a/rocket/src/main/scala/frontend.scala
+++ b/rocket/src/main/scala/frontend.scala
@@ -100,7 +100,6 @@ class Frontend(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePa
   icache.io.req.bits.kill := io.cpu.req.valid ||
     tlb.io.resp.miss || tlb.io.resp.xcpt_if ||
     icmiss || io.ptw.invalidate
-  icache.io.resp.ready := !stall && !s1_same_block
 
   io.cpu.resp.valid := s2_valid && (s2_xcpt_if || s2_resp_valid)
   io.cpu.resp.bits.pc := s2_pc
diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala
index e2ef913d..ca68a2b7 100644
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@@ -43,7 +43,7 @@ class ICache(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePara
   val rdy = Wire(Bool())
 
   val refill_addr = Reg(UInt(width = paddrBits))
-  val s1_any_tag_hit = Bool()
+  val s1_any_tag_hit = Wire(Bool())
 
   val s1_valid = Reg(init=Bool(false))
   val s1_pgoff = Reg(UInt(width = pgIdxBits))
@@ -77,7 +77,7 @@ class ICache(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePara
 
   val repl_way = if (isDM) UInt(0) else LFSR16(s1_miss)(log2Up(nWays)-1,0)
   val entagbits = code.width(tagBits)
-  val tag_array = SeqMem(Vec(Bits(width = entagbits), nWays), nSets)
+  val tag_array = SeqMem(nSets, Vec(nWays, Bits(width = entagbits)))
   val tag_rdata = tag_array.read(s0_pgoff(untagBits-1,blockOffBits), !refill_done && s0_valid)
   when (refill_done) {
     val tag = code.encode(refill_tag).toUInt
@@ -92,13 +92,13 @@ class ICache(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePara
     vb_array := Bits(0)
     invalidated := Bool(true)
   }
-  val s1_disparity = Vec.fill(nWays){Bool()}
+  val s1_disparity = Wire(Vec(nWays, Bool()))
   for (i <- 0 until nWays)
     when (s1_valid && s1_disparity(i)) { vb_array := vb_array.bitSet(Cat(UInt(i), s1_idx), Bool(false)) }
 
-  val s1_tag_match = Vec.fill(nWays){Bool()}
-  val s1_tag_hit = Vec.fill(nWays){Bool()}
-  val s1_dout = Vec.fill(nWays){(Bits())}
+  val s1_tag_match = Wire(Vec(nWays, Bool()))
+  val s1_tag_hit = Wire(Vec(nWays, Bool()))
+  val s1_dout = Wire(Vec(nWays, Bits(width = rowBits)))
 
   for (i <- 0 until nWays) {
     val s1_vb = !io.invalidate && vb_array(Cat(UInt(i), s1_pgoff(untagBits-1,blockOffBits))).toBool
@@ -113,7 +113,7 @@ class ICache(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePara
   s1_any_tag_hit := s1_tag_hit.reduceLeft(_||_) && !s1_disparity.reduceLeft(_||_)
 
   for (i <- 0 until nWays) {
-    val data_array = SeqMem(Bits(width = code.width(rowBits)), nSets*refillCycles)
+    val data_array = SeqMem(nSets * refillCycles, Bits(width = code.width(rowBits)))
     val wen = narrow_grant.valid && repl_way === UInt(i)
     when (wen) {
       val e_d = code.encode(narrow_grant.bits.data).toUInt