riscv/rocket-chip
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fix Chisel3 compat warnings in ICache and FPU

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This commit is contained in:
Howard Mao
2016-01-12 12:42:57 -08:00
parent 05b359d357
commit 13ce91e453
3 changed files with 8 additions and 9 deletions
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rocket/src/main/scala/fpu.scala
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@ -452,7 +452,7 @@ class FPU(implicit p: Parameters) extends CoreModule()(p) {
val fp_decoder = Module(new FPUDecoder)
fp_decoder.io.inst := io.inst
val cp_ctrl = new FPUCtrlSigs
val cp_ctrl = Wire(new FPUCtrlSigs)
cp_ctrl <> io.cp_req.bits
io.cp_resp.valid := Bool(false)
io.cp_resp.bits.data := UInt(0)