Debug: Annotate regmaps with RegFieldDescs
This commit is contained in:
Megan Wachs
parent
7abf6e1c8a
commit
13b120fb01
@ -89,7 +89,7 @@ import DebugModuleAccessType._
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object DebugAbstractCommandError extends scala.Enumeration {
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type DebugAbstractCommandError = Value
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val None, ErrBusy, ErrNotSupported, ErrException, ErrHaltResume = Value
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val Success, ErrBusy, ErrNotSupported, ErrException, ErrHaltResume = Value
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}
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import DebugAbstractCommandError._
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@ -250,18 +250,18 @@ class DebugCtrlBundle (nComponents: Int)(implicit val p: Parameters) extends Par
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// Local reg mapper function : Notify when written, but give the value as well.
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object WNotifyWire {
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def apply(n: Int, value: UInt, set: Bool) : RegField = {
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def apply(n: Int, value: UInt, set: Bool, name: String, desc: String) : RegField = {
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RegField(n, UInt(0), RegWriteFn((valid, data) => {
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set := valid
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value := data
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Bool(true)
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}))
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}), Some(RegFieldDesc(name = name, desc = desc, access = RegFieldAccessType.WSPECIAL)))
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}
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}
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// Local reg mapper function : Notify when accessed either as read or write.
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object RWNotify {
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def apply (n: Int, rVal: UInt, wVal: UInt, rNotify: Bool, wNotify: Bool) : RegField = {
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def apply (n: Int, rVal: UInt, wVal: UInt, rNotify: Bool, wNotify: Bool, desc: Option[RegFieldDesc] = None): RegField = {
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RegField(n,
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RegReadFn ((ready) => {rNotify := ready ; (Bool(true), rVal)}),
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RegWriteFn((valid, data) => {
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@ -269,7 +269,7 @@ object RWNotify {
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when (valid) {wVal := data}
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Bool(true)
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}
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))
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), desc)
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}
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}
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@ -344,7 +344,7 @@ class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyMod
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// DMCONTROL is the only register, so it's at offset 0.
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dmiNode.regmap(
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0 -> Seq(RWNotify(32, DMCONTROLRdData.asUInt(),
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DMCONTROLWrDataVal, DMCONTROLRdEn, DMCONTROLWrEn))
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DMCONTROLWrDataVal, DMCONTROLRdEn, DMCONTROLWrEn, Some(RegFieldDesc("dmi_dmcontrol", "", reset=Some(0)))))
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)
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//--------------------------------------------------------------
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@ -726,20 +726,25 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
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// Program Buffer Access (DMI ... System Bus can override)
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//--------------------------------------------------------------
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dmiNode.regmap(
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(DMI_DMSTATUS << 2) -> Seq(RegField.r(32, DMSTATUSRdData.asUInt())),
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(DMI_DMSTATUS << 2) -> Seq(RegField.r(32, DMSTATUSRdData.asUInt(), RegFieldDesc("dmi_dmstatus", ""))),
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//TODO (DMI_CFGSTRADDR0 << 2) -> cfgStrAddrFields,
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(DMI_HARTINFO << 2) -> Seq(RegField.r(32, HARTINFORdData.asUInt())),
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(DMI_HALTSUM << 2) -> Seq(RegField.r(32, HALTSUMRdData.asUInt())),
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(DMI_ABSTRACTCS << 2) -> Seq(RWNotify(32, ABSTRACTCSRdData.asUInt(), ABSTRACTCSWrDataVal, ABSTRACTCSRdEn, ABSTRACTCSWrEnMaybe)),
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(DMI_ABSTRACTAUTO<< 2) -> Seq(RWNotify(32, ABSTRACTAUTORdData.asUInt(), ABSTRACTAUTOWrDataVal, ABSTRACTAUTORdEn, ABSTRACTAUTOWrEnMaybe)),
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(DMI_COMMAND << 2) -> Seq(RWNotify(32, COMMANDRdData.asUInt(), COMMANDWrDataVal, COMMANDRdEn, COMMANDWrEnMaybe)),
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(DMI_DATA0 << 2) -> abstractDataMem.zipWithIndex.map{case (x, i) => RWNotify(8, x, abstractDataNxt(i),
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(DMI_HARTINFO << 2) -> Seq(RegField.r(32, HARTINFORdData.asUInt(), RegFieldDesc("dmi_hartinfo", "" /*, reset=Some(HARTINFORdData.litValue)*/))),
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(DMI_HALTSUM << 2) -> Seq(RegField.r(32, HALTSUMRdData.asUInt(), RegFieldDesc("dmi_haltsum", ""))),
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(DMI_ABSTRACTCS << 2) -> Seq(RWNotify(32, ABSTRACTCSRdData.asUInt(), ABSTRACTCSWrDataVal, ABSTRACTCSRdEn, ABSTRACTCSWrEnMaybe,
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Some(RegFieldDesc("dmi_abstractcs", "" /*, reset=Some(ABSTRACTCSReset.litValue)*/)))),
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(DMI_ABSTRACTAUTO<< 2) -> Seq(RWNotify(32, ABSTRACTAUTORdData.asUInt(), ABSTRACTAUTOWrDataVal, ABSTRACTAUTORdEn, ABSTRACTAUTOWrEnMaybe,
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Some(RegFieldDesc("dmi_abstractauto", "", reset=Some(0))))),
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(DMI_COMMAND << 2) -> Seq(RWNotify(32, COMMANDRdData.asUInt(), COMMANDWrDataVal, COMMANDRdEn, COMMANDWrEnMaybe,
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Some(RegFieldDesc("dmi_command", "", reset=Some(0))))),
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(DMI_DATA0 << 2) -> RegFieldGroup("dmi_data", None, abstractDataMem.zipWithIndex.map{case (x, i) => RWNotify(8, x, abstractDataNxt(i),
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dmiAbstractDataRdEn(i),
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dmiAbstractDataWrEnMaybe(i))},
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(DMI_PROGBUF0 << 2) -> programBufferMem.zipWithIndex.map{case (x, i) => RWNotify(8, x, programBufferNxt(i),
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dmiAbstractDataWrEnMaybe(i),
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Some(RegFieldDesc(s"dmi_data_$i", "", reset = Some(0))))}),
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(DMI_PROGBUF0 << 2) -> RegFieldGroup("dmi_progbuf", None, programBufferMem.zipWithIndex.map{case (x, i) => RWNotify(8, x, programBufferNxt(i),
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dmiProgramBufferRdEn(i),
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dmiProgramBufferWrEnMaybe(i))},
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(DMIConsts.dmi_haltStatusAddr << 2) -> haltedStatus.map(x => RegField.r(32, x))
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dmiProgramBufferWrEnMaybe(i),
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Some(RegFieldDesc(s"dmi_progbuf_$i", "", reset = Some(0))))}),
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(DMIConsts.dmi_haltStatusAddr << 2) -> RegFieldGroup("dmi_halt_status", None, haltedStatus.zipWithIndex.map{case (x, i) => RegField.r(32, x, RegFieldDesc(s"halt_status_$i", ""))})
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)
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abstractDataMem.zipWithIndex.foreach { case (x, i) =>
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@ -880,20 +885,28 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
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tlNode.regmap(
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// This memory is writable.
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HALTED -> Seq(WNotifyWire(sbIdWidth, hartHaltedId, hartHaltedWrEn)),
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GOING -> Seq(WNotifyWire(sbIdWidth, hartGoingId, hartGoingWrEn)),
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RESUMING -> Seq(WNotifyWire(sbIdWidth, hartResumingId, hartResumingWrEn)),
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EXCEPTION -> Seq(WNotifyWire(sbIdWidth, hartExceptionId, hartExceptionWrEn)),
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DATA -> abstractDataMem.map(x => RegField(8, x)),
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PROGBUF(cfg)-> programBufferMem.map(x => RegField(8, x)),
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HALTED -> Seq(WNotifyWire(sbIdWidth, hartHaltedId, hartHaltedWrEn,
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"debug_hart_halted", "Debug ROM Causes hart to write its hartID here when it is in Debug Mode.")),
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GOING -> Seq(WNotifyWire(sbIdWidth, hartGoingId, hartGoingWrEn,
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"debug_hart_going", "Debug ROM causes hart to write 0 here when it begins executing Debug Mode instructions.")),
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RESUMING -> Seq(WNotifyWire(sbIdWidth, hartResumingId, hartResumingWrEn,
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"debug_hart_resuming", "Debug ROM causes hart to write 0 here when it leaves Debug Mode.")),
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EXCEPTION -> Seq(WNotifyWire(sbIdWidth, hartExceptionId, hartExceptionWrEn,
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"debug_hart_exception", "Debug ROM causes hart to write 0 here if it gets an exception in Debug Mode.")),
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DATA -> RegFieldGroup("debug_data", Some("Data used to communicate with Debug Module"),
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abstractDataMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_data_$i", ""))}),
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PROGBUF(cfg)-> RegFieldGroup("debug_progbuf", Some("Program buffer used to communicate with Debug Module"),
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programBufferMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_progbuf_$i", ""))}),
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// These sections are read-only.
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IMPEBREAK(cfg)-> {if (cfg.hasImplicitEbreak) Seq(RegField.r(32, Instructions.EBREAK.value.U)) else Nil},
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WHERETO -> Seq(RegField.r(32, jalAbstract.asUInt)),
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ABSTRACT(cfg) -> abstractGeneratedMem.map{x => RegField.r(32, x)},
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FLAGS -> flags.map{x => RegField.r(8, x.asUInt())},
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ROMBASE -> DebugRomContents().map(x => RegField.r(8, (x & 0xFF).U(8.W)))
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IMPEBREAK(cfg)-> {if (cfg.hasImplicitEbreak) Seq(RegField.r(32, Instructions.EBREAK.value.U, RegFieldDesc("debug_impebreak", "Debug Implicit EBREAK"))) else Nil},
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WHERETO -> Seq(RegField.r(32, jalAbstract.asUInt, RegFieldDesc("debug_whereto", "Instruction filled in by Debug Module to control hart in Debug Mode"))),
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ABSTRACT(cfg) -> RegFieldGroup("debug_abstract", Some("Instructions generated by Debug Module"),
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abstractGeneratedMem.zipWithIndex.map{ case (x,i) => RegField.r(32, x, RegFieldDesc(s"debug_abstract_$i", ""))}),
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FLAGS -> RegFieldGroup("debug_flags", Some("Memory region used to control hart going/resuming in Debug Mode"),
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flags.zipWithIndex.map{case(x, i) => RegField.r(8, x.asUInt(), RegFieldDesc(s"debug_flags_$i", ""))}),
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ROMBASE -> RegFieldGroup("debug_rom", Some("Debug ROM"),
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DebugRomContents().zipWithIndex.map{case (x, i) => RegField.r(8, (x & 0xFF).U(8.W), RegFieldDesc(s"debug_rom_$i", "", reset=Some(x)))})
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)
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// Override System Bus accesses with dmactive reset.
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