From 13b120fb0144e19f9eb9db74276fd452c50d806a Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Sat, 10 Feb 2018 20:11:24 -0800 Subject: [PATCH] Debug: Annotate regmaps with RegFieldDescs --- src/main/scala/devices/debug/Debug.scala | 71 ++++++++++++++---------- 1 file changed, 42 insertions(+), 29 deletions(-) diff --git a/src/main/scala/devices/debug/Debug.scala b/src/main/scala/devices/debug/Debug.scala index 9167a715..5e0c3fc6 100644 --- a/src/main/scala/devices/debug/Debug.scala +++ b/src/main/scala/devices/debug/Debug.scala @@ -89,7 +89,7 @@ import DebugModuleAccessType._ object DebugAbstractCommandError extends scala.Enumeration { type DebugAbstractCommandError = Value - val None, ErrBusy, ErrNotSupported, ErrException, ErrHaltResume = Value + val Success, ErrBusy, ErrNotSupported, ErrException, ErrHaltResume = Value } import DebugAbstractCommandError._ @@ -250,18 +250,18 @@ class DebugCtrlBundle (nComponents: Int)(implicit val p: Parameters) extends Par // Local reg mapper function : Notify when written, but give the value as well. object WNotifyWire { - def apply(n: Int, value: UInt, set: Bool) : RegField = { + def apply(n: Int, value: UInt, set: Bool, name: String, desc: String) : RegField = { RegField(n, UInt(0), RegWriteFn((valid, data) => { set := valid value := data Bool(true) - })) + }), Some(RegFieldDesc(name = name, desc = desc, access = RegFieldAccessType.WSPECIAL))) } } // Local reg mapper function : Notify when accessed either as read or write. object RWNotify { - def apply (n: Int, rVal: UInt, wVal: UInt, rNotify: Bool, wNotify: Bool) : RegField = { + def apply (n: Int, rVal: UInt, wVal: UInt, rNotify: Bool, wNotify: Bool, desc: Option[RegFieldDesc] = None): RegField = { RegField(n, RegReadFn ((ready) => {rNotify := ready ; (Bool(true), rVal)}), RegWriteFn((valid, data) => { @@ -269,7 +269,7 @@ object RWNotify { when (valid) {wVal := data} Bool(true) } - )) + ), desc) } } @@ -344,7 +344,7 @@ class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyMod // DMCONTROL is the only register, so it's at offset 0. dmiNode.regmap( 0 -> Seq(RWNotify(32, DMCONTROLRdData.asUInt(), - DMCONTROLWrDataVal, DMCONTROLRdEn, DMCONTROLWrEn)) + DMCONTROLWrDataVal, DMCONTROLRdEn, DMCONTROLWrEn, Some(RegFieldDesc("dmi_dmcontrol", "", reset=Some(0))))) ) //-------------------------------------------------------------- @@ -726,20 +726,25 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p: // Program Buffer Access (DMI ... System Bus can override) //-------------------------------------------------------------- dmiNode.regmap( - (DMI_DMSTATUS << 2) -> Seq(RegField.r(32, DMSTATUSRdData.asUInt())), + (DMI_DMSTATUS << 2) -> Seq(RegField.r(32, DMSTATUSRdData.asUInt(), RegFieldDesc("dmi_dmstatus", ""))), //TODO (DMI_CFGSTRADDR0 << 2) -> cfgStrAddrFields, - (DMI_HARTINFO << 2) -> Seq(RegField.r(32, HARTINFORdData.asUInt())), - (DMI_HALTSUM << 2) -> Seq(RegField.r(32, HALTSUMRdData.asUInt())), - (DMI_ABSTRACTCS << 2) -> Seq(RWNotify(32, ABSTRACTCSRdData.asUInt(), ABSTRACTCSWrDataVal, ABSTRACTCSRdEn, ABSTRACTCSWrEnMaybe)), - (DMI_ABSTRACTAUTO<< 2) -> Seq(RWNotify(32, ABSTRACTAUTORdData.asUInt(), ABSTRACTAUTOWrDataVal, ABSTRACTAUTORdEn, ABSTRACTAUTOWrEnMaybe)), - (DMI_COMMAND << 2) -> Seq(RWNotify(32, COMMANDRdData.asUInt(), COMMANDWrDataVal, COMMANDRdEn, COMMANDWrEnMaybe)), - (DMI_DATA0 << 2) -> abstractDataMem.zipWithIndex.map{case (x, i) => RWNotify(8, x, abstractDataNxt(i), + (DMI_HARTINFO << 2) -> Seq(RegField.r(32, HARTINFORdData.asUInt(), RegFieldDesc("dmi_hartinfo", "" /*, reset=Some(HARTINFORdData.litValue)*/))), + (DMI_HALTSUM << 2) -> Seq(RegField.r(32, HALTSUMRdData.asUInt(), RegFieldDesc("dmi_haltsum", ""))), + (DMI_ABSTRACTCS << 2) -> Seq(RWNotify(32, ABSTRACTCSRdData.asUInt(), ABSTRACTCSWrDataVal, ABSTRACTCSRdEn, ABSTRACTCSWrEnMaybe, + Some(RegFieldDesc("dmi_abstractcs", "" /*, reset=Some(ABSTRACTCSReset.litValue)*/)))), + (DMI_ABSTRACTAUTO<< 2) -> Seq(RWNotify(32, ABSTRACTAUTORdData.asUInt(), ABSTRACTAUTOWrDataVal, ABSTRACTAUTORdEn, ABSTRACTAUTOWrEnMaybe, + Some(RegFieldDesc("dmi_abstractauto", "", reset=Some(0))))), + (DMI_COMMAND << 2) -> Seq(RWNotify(32, COMMANDRdData.asUInt(), COMMANDWrDataVal, COMMANDRdEn, COMMANDWrEnMaybe, + Some(RegFieldDesc("dmi_command", "", reset=Some(0))))), + (DMI_DATA0 << 2) -> RegFieldGroup("dmi_data", None, abstractDataMem.zipWithIndex.map{case (x, i) => RWNotify(8, x, abstractDataNxt(i), dmiAbstractDataRdEn(i), - dmiAbstractDataWrEnMaybe(i))}, - (DMI_PROGBUF0 << 2) -> programBufferMem.zipWithIndex.map{case (x, i) => RWNotify(8, x, programBufferNxt(i), + dmiAbstractDataWrEnMaybe(i), + Some(RegFieldDesc(s"dmi_data_$i", "", reset = Some(0))))}), + (DMI_PROGBUF0 << 2) -> RegFieldGroup("dmi_progbuf", None, programBufferMem.zipWithIndex.map{case (x, i) => RWNotify(8, x, programBufferNxt(i), dmiProgramBufferRdEn(i), - dmiProgramBufferWrEnMaybe(i))}, - (DMIConsts.dmi_haltStatusAddr << 2) -> haltedStatus.map(x => RegField.r(32, x)) + dmiProgramBufferWrEnMaybe(i), + Some(RegFieldDesc(s"dmi_progbuf_$i", "", reset = Some(0))))}), + (DMIConsts.dmi_haltStatusAddr << 2) -> RegFieldGroup("dmi_halt_status", None, haltedStatus.zipWithIndex.map{case (x, i) => RegField.r(32, x, RegFieldDesc(s"halt_status_$i", ""))}) ) abstractDataMem.zipWithIndex.foreach { case (x, i) => @@ -880,20 +885,28 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p: tlNode.regmap( // This memory is writable. - HALTED -> Seq(WNotifyWire(sbIdWidth, hartHaltedId, hartHaltedWrEn)), - GOING -> Seq(WNotifyWire(sbIdWidth, hartGoingId, hartGoingWrEn)), - RESUMING -> Seq(WNotifyWire(sbIdWidth, hartResumingId, hartResumingWrEn)), - EXCEPTION -> Seq(WNotifyWire(sbIdWidth, hartExceptionId, hartExceptionWrEn)), - DATA -> abstractDataMem.map(x => RegField(8, x)), - PROGBUF(cfg)-> programBufferMem.map(x => RegField(8, x)), + HALTED -> Seq(WNotifyWire(sbIdWidth, hartHaltedId, hartHaltedWrEn, + "debug_hart_halted", "Debug ROM Causes hart to write its hartID here when it is in Debug Mode.")), + GOING -> Seq(WNotifyWire(sbIdWidth, hartGoingId, hartGoingWrEn, + "debug_hart_going", "Debug ROM causes hart to write 0 here when it begins executing Debug Mode instructions.")), + RESUMING -> Seq(WNotifyWire(sbIdWidth, hartResumingId, hartResumingWrEn, + "debug_hart_resuming", "Debug ROM causes hart to write 0 here when it leaves Debug Mode.")), + EXCEPTION -> Seq(WNotifyWire(sbIdWidth, hartExceptionId, hartExceptionWrEn, + "debug_hart_exception", "Debug ROM causes hart to write 0 here if it gets an exception in Debug Mode.")), + DATA -> RegFieldGroup("debug_data", Some("Data used to communicate with Debug Module"), + abstractDataMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_data_$i", ""))}), + PROGBUF(cfg)-> RegFieldGroup("debug_progbuf", Some("Program buffer used to communicate with Debug Module"), + programBufferMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_progbuf_$i", ""))}), // These sections are read-only. - IMPEBREAK(cfg)-> {if (cfg.hasImplicitEbreak) Seq(RegField.r(32, Instructions.EBREAK.value.U)) else Nil}, - WHERETO -> Seq(RegField.r(32, jalAbstract.asUInt)), - ABSTRACT(cfg) -> abstractGeneratedMem.map{x => RegField.r(32, x)}, - FLAGS -> flags.map{x => RegField.r(8, x.asUInt())}, - ROMBASE -> DebugRomContents().map(x => RegField.r(8, (x & 0xFF).U(8.W))) - + IMPEBREAK(cfg)-> {if (cfg.hasImplicitEbreak) Seq(RegField.r(32, Instructions.EBREAK.value.U, RegFieldDesc("debug_impebreak", "Debug Implicit EBREAK"))) else Nil}, + WHERETO -> Seq(RegField.r(32, jalAbstract.asUInt, RegFieldDesc("debug_whereto", "Instruction filled in by Debug Module to control hart in Debug Mode"))), + ABSTRACT(cfg) -> RegFieldGroup("debug_abstract", Some("Instructions generated by Debug Module"), + abstractGeneratedMem.zipWithIndex.map{ case (x,i) => RegField.r(32, x, RegFieldDesc(s"debug_abstract_$i", ""))}), + FLAGS -> RegFieldGroup("debug_flags", Some("Memory region used to control hart going/resuming in Debug Mode"), + flags.zipWithIndex.map{case(x, i) => RegField.r(8, x.asUInt(), RegFieldDesc(s"debug_flags_$i", ""))}), + ROMBASE -> RegFieldGroup("debug_rom", Some("Debug ROM"), + DebugRomContents().zipWithIndex.map{case (x, i) => RegField.r(8, (x & 0xFF).U(8.W), RegFieldDesc(s"debug_rom_$i", "", reset=Some(x)))}) ) // Override System Bus accesses with dmactive reset.