refactor cpfences
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4121fb178c
commit
137fd62007
@ -600,32 +600,13 @@ class rocketCtrl extends Component
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val vec = new rocketCtrlVec()
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val vec = new rocketCtrlVec()
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io.vec_dpath <> vec.io.dpath
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io.vec_dpath <> vec.io.dpath
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io.vec_iface <> vec.io.iface
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io.vec_iface.vcmdq_valid := vec.io.iface.vcmdq_valid
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vec.io.sr_ev := io.dpath.status(SR_EV)
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io.vec_iface.vximm1q_valid := vec.io.iface.vximm1q_valid
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vec.io.exception := wb_reg_exception
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io.vec_iface.vximm2q_valid := vec.io.iface.vximm2q_valid
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vec.io.iface.vcmdq_ready := io.vec_iface.vcmdq_ready
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vec.io.iface.vximm1q_ready := io.vec_iface.vximm1q_ready
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vec.io.iface.vximm2q_ready := io.vec_iface.vximm2q_ready
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io.vec_iface.vpfcmdq_valid := vec.io.iface.vpfcmdq_valid
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io.vec_iface.vpfximm1q_valid := vec.io.iface.vpfximm1q_valid
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io.vec_iface.vpfximm2q_valid := vec.io.iface.vpfximm2q_valid
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vec.io.iface.vpfcmdq_ready := io.vec_iface.vpfcmdq_ready
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vec.io.iface.vpfximm1q_ready := io.vec_iface.vpfximm1q_ready
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vec.io.iface.vpfximm2q_ready := io.vec_iface.vpfximm2q_ready
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vec_replay = vec.io.replay
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vec_replay = vec.io.replay
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vec_cpfence = Reg(resetVal = Bool(false))
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vec_cpfence = vec.io.cpfence
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when (vec.io.cpfence) {
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vec_cpfence := Bool(true)
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}
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when (io.vec_iface.vackq_valid || wb_reg_exception) {
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vec_cpfence := Bool(false)
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}
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io.vec_iface.vackq_ready := Bool(true)
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vec.io.sr_ev := io.dpath.status(SR_EV)
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}
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}
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// exception handling
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// exception handling
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@ -41,6 +41,7 @@ class ioCtrlVec extends Bundle
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val dpath = new ioCtrlDpathVec()
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val dpath = new ioCtrlDpathVec()
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val iface = new ioCtrlVecInterface()
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val iface = new ioCtrlVecInterface()
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val sr_ev = Bool(INPUT)
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val sr_ev = Bool(INPUT)
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val exception = Bool(INPUT)
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val replay = Bool(OUTPUT)
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val replay = Bool(OUTPUT)
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val cpfence = Bool(OUTPUT)
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val cpfence = Bool(OUTPUT)
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}
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}
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@ -151,6 +152,8 @@ class rocketCtrlVec extends Component
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mask_wb_vec_cmdq_ready && mask_wb_vec_ximm1q_ready && mask_wb_vec_ximm2q_ready &&
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mask_wb_vec_cmdq_ready && mask_wb_vec_ximm1q_ready && mask_wb_vec_ximm2q_ready &&
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mask_wb_vec_pfcmdq_ready && mask_wb_vec_pfximm1q_ready && wb_vec_pfximm2q_enq
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mask_wb_vec_pfcmdq_ready && mask_wb_vec_pfximm1q_ready && wb_vec_pfximm2q_enq
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io.iface.vackq_ready := Bool(true)
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io.replay := valid_common && (
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io.replay := valid_common && (
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wb_vec_cmdq_enq && !io.iface.vcmdq_ready ||
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wb_vec_cmdq_enq && !io.iface.vcmdq_ready ||
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wb_vec_ximm1q_enq && !io.iface.vximm1q_ready ||
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wb_vec_ximm1q_enq && !io.iface.vximm1q_ready ||
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@ -159,5 +162,12 @@ class rocketCtrlVec extends Component
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wb_vec_pfximm1q_enq && !io.iface.vpfximm1q_ready ||
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wb_vec_pfximm1q_enq && !io.iface.vpfximm1q_ready ||
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wb_vec_pfximm2q_enq && !io.iface.vpfximm2q_ready
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wb_vec_pfximm2q_enq && !io.iface.vpfximm2q_ready
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)
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)
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io.cpfence := valid_common && wb_vec_cpfence && !io.replay
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val reg_cpfence = Reg(resetVal = Bool(false))
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val do_cpfence = valid_common && wb_vec_cpfence && !io.replay
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when (do_cpfence) { reg_cpfence := Bool(true) }
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when (io.iface.vackq_valid || io.exception) { reg_cpfence := Bool(false) }
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io.cpfence := reg_cpfence
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}
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}
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