riscv/rocket-chip
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Merge remote-tracking branch 'origin/master' into async_reg

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Megan Wachs 2017-09-07 11:27:36 -07:00
commit 1320f65ae6
1 changed files with 6 additions and 5 deletions
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11
vsrc/jtag_vpi.v
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@ -42,7 +42,8 @@ module JTAGVPI
#( parameter DEBUG_INFO = 0, #( parameter DEBUG_INFO = 0,
parameter TP = 1, parameter TP = 1,
parameter TCK_HALF_PERIOD = 2,// 50, // Clock half period (Clock period = 100 ns => 10 MHz) parameter TCK_HALF_PERIOD = 2,// 50, // Clock half period (Clock period = 100 ns => 10 MHz)
parameter CMD_DELAY = 2 // 1000 parameter CMD_DELAY = 2, // 1000
parameter INIT_DELAY = 200
) )
( (
output jtag_TMS, output jtag_TMS,
@ -87,10 +88,10 @@ begin
data_out <= 32'h0; data_out <= 32'h0;
data_in <= 32'h0; data_in <= 32'h0;
// Insert a #delay here because we need to // Small delay to get past reset instability
// wait until the PC isn't pointing to flash anymore // before checking for init_done
// (this is around 20k ns if the flash_crash boot code #INIT_DELAY
// is being booted from, else much bigger, around 10mil ns)
wait(init_done) wait(init_done)
if($test$plusargs("jtag_vpi_enable")) main; if($test$plusargs("jtag_vpi_enable")) main;
end end