From 19eabb672897e4f07683bdc2966f4242ebdd84f9 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Wed, 6 Sep 2017 18:13:04 -0700
Subject: [PATCH 1/2] jtag_vpi: add some hysterisis for waiting for init_done

---
 vsrc/jtag_vpi.v | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/vsrc/jtag_vpi.v b/vsrc/jtag_vpi.v
index c2d83438..c9b53aef 100644
--- a/vsrc/jtag_vpi.v
+++ b/vsrc/jtag_vpi.v
@@ -87,10 +87,10 @@ begin
 	data_out	<= 32'h0;
 	data_in		<= 32'h0;
 
-	// Insert a #delay here because we need to
-	// wait until the PC isn't pointing to flash anymore
-	// (this is around 20k ns if the flash_crash boot code
-	// is being booted from, else much bigger, around 10mil ns)
+        // Small delay to get past reset instability
+        //  before checking for init_done
+        #200 
+          
 	wait(init_done)
 		if($test$plusargs("jtag_vpi_enable")) main;
 end

From f68390e4585bfa1891660b5176980e53c438c7b9 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Thu, 7 Sep 2017 09:06:07 -0700
Subject: [PATCH 2/2] jtag_vpi: Use a parameter for INIT_DELAY vs constant

---
 vsrc/jtag_vpi.v | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/vsrc/jtag_vpi.v b/vsrc/jtag_vpi.v
index c9b53aef..45d426b1 100644
--- a/vsrc/jtag_vpi.v
+++ b/vsrc/jtag_vpi.v
@@ -42,7 +42,8 @@ module JTAGVPI
 #(	parameter DEBUG_INFO = 0,
 	parameter TP = 1,
 	parameter TCK_HALF_PERIOD = 2,// 50, // Clock half period (Clock period = 100 ns => 10 MHz)
-        parameter  CMD_DELAY = 2 // 1000
+        parameter CMD_DELAY = 2, // 1000
+        parameter INIT_DELAY = 200
 )   
 (
 	output jtag_TMS,
@@ -89,7 +90,7 @@ begin
 
         // Small delay to get past reset instability
         //  before checking for init_done
-        #200 
+        #INIT_DELAY 
           
 	wait(init_done)
 		if($test$plusargs("jtag_vpi_enable")) main;