riscv/rocket-chip
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Preserve id_do_fence (#651)

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solomatnikov 2017-04-05 08:29:45 -07:00 committed by GitHub
parent 19f0ae64a0
commit 127f121ef2
1 changed files with 2 additions and 2 deletions
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src/main/scala/rocket/Rocket.scala
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@ -217,8 +217,8 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
val id_rocc_busy = Bool(usingRoCC) && val id_rocc_busy = Bool(usingRoCC) &&
(io.rocc.busy || ex_reg_valid && ex_ctrl.rocc || (io.rocc.busy || ex_reg_valid && ex_ctrl.rocc ||
mem_reg_valid && mem_ctrl.rocc || wb_reg_valid && wb_ctrl.rocc) mem_reg_valid && mem_ctrl.rocc || wb_reg_valid && wb_ctrl.rocc)
val id_do_fence = id_rocc_busy && id_ctrl.fence || val id_do_fence = Wire(init = id_rocc_busy && id_ctrl.fence ||
id_mem_busy && (id_ctrl.amo && id_amo_aq || id_ctrl.fence_i || id_reg_fence && (id_ctrl.mem || id_ctrl.rocc)) id_mem_busy && (id_ctrl.amo && id_amo_aq || id_ctrl.fence_i || id_reg_fence && (id_ctrl.mem || id_ctrl.rocc)))
val bpu = Module(new BreakpointUnit(nBreakpoints)) val bpu = Module(new BreakpointUnit(nBreakpoints))
bpu.io.status := csr.io.status bpu.io.status := csr.io.status