riscv/rocket-chip
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fix more Chisel3 deprecations

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This commit is contained in:
Howard Mao
2016-01-14 13:57:45 -08:00
parent d51c127646
commit 120361226d
9 changed files with 37 additions and 37 deletions
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4
rocket/src/main/scala/ptw.scala
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@ -54,7 +54,7 @@ class PTE(implicit p: Parameters) extends CoreBundle()(p) {
class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
val io = new Bundle {
val requestor = Vec(new TLBPTWIO, n).flip
val requestor = Vec(n, new TLBPTWIO).flip
val mem = new HellaCacheIO
val dpath = new DatapathPTWIO
}
@ -85,7 +85,7 @@ class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
val (pte_cache_hit, pte_cache_data) = {
val size = log2Up(pgLevels * 2)
val plru = new PseudoLRU(size)
val valid = Reg(Vec(Bool(), size))
val valid = Reg(Vec(size, Bool()))
val validBits = valid.toBits
val tags = Mem(size, UInt(width = paddrBits))
val data = Mem(size, UInt(width = ppnBits))