riscv/rocket-chip
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fix more Chisel3 deprecations

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Howard Mao
2016-01-14 13:57:45 -08:00
parent d51c127646
commit 120361226d
9 changed files with 37 additions and 37 deletions
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rocket/src/main/scala/frontend.scala
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@ -11,7 +11,7 @@ class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) {
class FrontendResp(implicit p: Parameters) extends CoreBundle()(p) {
val pc = UInt(width = vaddrBitsExtended) // ID stage PC
val data = Vec(Bits(width = coreInstBits), fetchWidth)
val data = Vec(fetchWidth, Bits(width = coreInstBits))
val mask = Bits(width = fetchWidth)
val xcpt_if = Bool()
}