riscv/rocket-chip
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more cleanup

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This commit is contained in:
Rimas Avizienis 2011-11-18 00:17:30 -08:00
parent c42d8149b7
commit 11f0e3daf4
3 changed files with 5 additions and 14 deletions
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3
rocket/src/main/scala/cpu.scala
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@ -7,9 +7,6 @@ import Constants._;
class ioDebug(view: List[String] = null) extends Bundle(view) class ioDebug(view: List[String] = null) extends Bundle(view)
{ {
val error_mode = Bool('output); val error_mode = Bool('output);
val id_valid = Bool('output);
val ex_valid = Bool('output);
val mem_valid = Bool('output);
} }
class ioHost(view: List[String] = null) extends Bundle(view) class ioHost(view: List[String] = null) extends Bundle(view)

10
rocket/src/main/scala/ctrl.scala
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@ -330,7 +330,7 @@ class rocketCtrl extends Component
val ex_reg_br_type = Reg(){UFix(width = 4)}; val ex_reg_br_type = Reg(){UFix(width = 4)};
val ex_reg_btb_hit = Reg(){Bool()}; val ex_reg_btb_hit = Reg(){Bool()};
val ex_reg_inst_div_mul_val = Reg(){Bool()}; val ex_reg_div_mul_val = Reg(){Bool()};
val ex_reg_mem_val = Reg(){Bool()}; val ex_reg_mem_val = Reg(){Bool()};
val ex_reg_mem_cmd = Reg(){UFix(width = 4)}; val ex_reg_mem_cmd = Reg(){UFix(width = 4)};
val ex_reg_mem_type = Reg(){UFix(width = 3)}; val ex_reg_mem_type = Reg(){UFix(width = 3)};
@ -376,7 +376,7 @@ class rocketCtrl extends Component
when (reset.toBool || io.dpath.killd) { when (reset.toBool || io.dpath.killd) {
ex_reg_br_type <== BR_N; ex_reg_br_type <== BR_N;
ex_reg_btb_hit <== Bool(false); ex_reg_btb_hit <== Bool(false);
ex_reg_inst_div_mul_val <== Bool(false); ex_reg_div_mul_val <== Bool(false);
ex_reg_mem_val <== Bool(false); ex_reg_mem_val <== Bool(false);
ex_reg_mem_cmd <== UFix(0, 4); ex_reg_mem_cmd <== UFix(0, 4);
ex_reg_mem_type <== UFix(0, 3); ex_reg_mem_type <== UFix(0, 3);
@ -395,7 +395,7 @@ class rocketCtrl extends Component
otherwise { otherwise {
ex_reg_br_type <== id_br_type; ex_reg_br_type <== id_br_type;
ex_reg_btb_hit <== id_reg_btb_hit; ex_reg_btb_hit <== id_reg_btb_hit;
ex_reg_inst_div_mul_val <== id_div_val.toBool || id_mul_val.toBool; ex_reg_div_mul_val <== id_div_val.toBool || id_mul_val.toBool;
ex_reg_mem_val <== id_mem_val.toBool; ex_reg_mem_val <== id_mem_val.toBool;
ex_reg_mem_cmd <== id_mem_cmd; ex_reg_mem_cmd <== id_mem_cmd;
ex_reg_mem_type <== id_mem_type; ex_reg_mem_type <== id_mem_type;
@ -460,7 +460,7 @@ class rocketCtrl extends Component
mem_reg_xcpt_syscall <== Bool(false); mem_reg_xcpt_syscall <== Bool(false);
} }
otherwise { otherwise {
mem_reg_div_mul_val <== ex_reg_inst_div_mul_val; mem_reg_div_mul_val <== ex_reg_div_mul_val;
mem_reg_eret <== ex_reg_eret; mem_reg_eret <== ex_reg_eret;
mem_reg_mem_val <== ex_reg_mem_val; mem_reg_mem_val <== ex_reg_mem_val;
mem_reg_mem_cmd <== ex_reg_mem_cmd; mem_reg_mem_cmd <== ex_reg_mem_cmd;
@ -592,7 +592,7 @@ class rocketCtrl extends Component
// check for divide and multiply instructions in ex,mem,wb stages // check for divide and multiply instructions in ex,mem,wb stages
val dm_stall_ex = val dm_stall_ex =
ex_reg_inst_div_mul_val && ex_reg_div_mul_val &&
((id_ren1.toBool && (id_raddr1 === io.dpath.ex_waddr)) || ((id_ren1.toBool && (id_raddr1 === io.dpath.ex_waddr)) ||
(id_ren2.toBool && (id_raddr2 === io.dpath.ex_waddr))); (id_ren2.toBool && (id_raddr2 === io.dpath.ex_waddr)));

6
rocket/src/main/scala/dpath.scala
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@ -445,12 +445,6 @@ class rocketDpath extends Component
pcr.io.cause := io.ctrl.cause; pcr.io.cause := io.ctrl.cause;
pcr.io.pc := mem_reg_pc; pcr.io.pc := mem_reg_pc;
pcr.io.badvaddr_wen := io.ctrl.badvaddr_wen; pcr.io.badvaddr_wen := io.ctrl.badvaddr_wen;
// temporary debug outputs so things don't get optimized away
io.debug.id_valid := id_reg_valid;
io.debug.ex_valid := ex_reg_valid;
io.debug.mem_valid := mem_reg_valid;
} }
} }