From 11f0e3daf45063ab67968f0bd3db2749124c6776 Mon Sep 17 00:00:00 2001 From: Rimas Avizienis Date: Fri, 18 Nov 2011 00:17:30 -0800 Subject: [PATCH] more cleanup --- rocket/src/main/scala/cpu.scala | 3 --- rocket/src/main/scala/ctrl.scala | 10 +++++----- rocket/src/main/scala/dpath.scala | 6 ------ 3 files changed, 5 insertions(+), 14 deletions(-) diff --git a/rocket/src/main/scala/cpu.scala b/rocket/src/main/scala/cpu.scala index 0d46f702..e38f3813 100644 --- a/rocket/src/main/scala/cpu.scala +++ b/rocket/src/main/scala/cpu.scala @@ -7,9 +7,6 @@ import Constants._; class ioDebug(view: List[String] = null) extends Bundle(view) { val error_mode = Bool('output); - val id_valid = Bool('output); - val ex_valid = Bool('output); - val mem_valid = Bool('output); } class ioHost(view: List[String] = null) extends Bundle(view) diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala index be527aa5..680a68f7 100644 --- a/rocket/src/main/scala/ctrl.scala +++ b/rocket/src/main/scala/ctrl.scala @@ -330,7 +330,7 @@ class rocketCtrl extends Component val ex_reg_br_type = Reg(){UFix(width = 4)}; val ex_reg_btb_hit = Reg(){Bool()}; - val ex_reg_inst_div_mul_val = Reg(){Bool()}; + val ex_reg_div_mul_val = Reg(){Bool()}; val ex_reg_mem_val = Reg(){Bool()}; val ex_reg_mem_cmd = Reg(){UFix(width = 4)}; val ex_reg_mem_type = Reg(){UFix(width = 3)}; @@ -376,7 +376,7 @@ class rocketCtrl extends Component when (reset.toBool || io.dpath.killd) { ex_reg_br_type <== BR_N; ex_reg_btb_hit <== Bool(false); - ex_reg_inst_div_mul_val <== Bool(false); + ex_reg_div_mul_val <== Bool(false); ex_reg_mem_val <== Bool(false); ex_reg_mem_cmd <== UFix(0, 4); ex_reg_mem_type <== UFix(0, 3); @@ -395,7 +395,7 @@ class rocketCtrl extends Component otherwise { ex_reg_br_type <== id_br_type; ex_reg_btb_hit <== id_reg_btb_hit; - ex_reg_inst_div_mul_val <== id_div_val.toBool || id_mul_val.toBool; + ex_reg_div_mul_val <== id_div_val.toBool || id_mul_val.toBool; ex_reg_mem_val <== id_mem_val.toBool; ex_reg_mem_cmd <== id_mem_cmd; ex_reg_mem_type <== id_mem_type; @@ -460,7 +460,7 @@ class rocketCtrl extends Component mem_reg_xcpt_syscall <== Bool(false); } otherwise { - mem_reg_div_mul_val <== ex_reg_inst_div_mul_val; + mem_reg_div_mul_val <== ex_reg_div_mul_val; mem_reg_eret <== ex_reg_eret; mem_reg_mem_val <== ex_reg_mem_val; mem_reg_mem_cmd <== ex_reg_mem_cmd; @@ -592,7 +592,7 @@ class rocketCtrl extends Component // check for divide and multiply instructions in ex,mem,wb stages val dm_stall_ex = - ex_reg_inst_div_mul_val && + ex_reg_div_mul_val && ((id_ren1.toBool && (id_raddr1 === io.dpath.ex_waddr)) || (id_ren2.toBool && (id_raddr2 === io.dpath.ex_waddr))); diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala index 4192cbd3..97a9af33 100644 --- a/rocket/src/main/scala/dpath.scala +++ b/rocket/src/main/scala/dpath.scala @@ -445,12 +445,6 @@ class rocketDpath extends Component pcr.io.cause := io.ctrl.cause; pcr.io.pc := mem_reg_pc; pcr.io.badvaddr_wen := io.ctrl.badvaddr_wen; - - // temporary debug outputs so things don't get optimized away - io.debug.id_valid := id_reg_valid; - io.debug.ex_valid := ex_reg_valid; - io.debug.mem_valid := mem_reg_valid; - } }