riscv/rocket-chip
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Fix tests when !hwacha; disable hwacha by default

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This commit is contained in:
Andrew Waterman
2014-02-06 03:08:33 -08:00
parent e20de64b8c
commit 11e69a73cd
6 changed files with 6 additions and 8 deletions
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2
chisel

Submodule chisel updated: 13f7e13730...213d7d6fc5

2
hardfloat

Submodule hardfloat updated: ac7ec37adf...d126925915

2
riscv-tests

Submodule riscv-tests updated: 6fdd12c130...e5d9d1af2e

2
riscv-tools

Submodule riscv-tools updated: 76441991a8...3338089dbd

2
rocket

Submodule rocket updated: 42f215b37a...08cd734296

4
src/main/scala/RocketChip.scala
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@@ -257,9 +257,7 @@ class Top extends Module {
val vic = ICacheConfig(128, 1)
val hc = hwacha.HwachaConfiguration(vic, 8, 256, ndtlb = 8, nptlb = 2)
val rc = RocketConfiguration(tl, ic, dc,
fpu = HAS_FPU,
rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c))
)
fpu = HAS_FPU)
val io = new VLSITopIO(HTIF_WIDTH)