riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Fix tests when !hwacha; disable hwacha by default

Browse Source
This commit is contained in:
Andrew Waterman 2014-02-06 03:08:33 -08:00
parent e20de64b8c
commit 11e69a73cd
6 changed files with 6 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
chisel

@ -1 +1 @@
Subproject commit 13f7e13730657c370ab0a91f5bf046661f4a8359 Subproject commit 213d7d6fc5a5d35c3665490b955a64aacf3a354d

2
hardfloat

@ -1 +1 @@
Subproject commit ac7ec37adf725caf9291d813e46826a9a7cab22c Subproject commit d1269259151b25e7a7a1ddc22bf85b92cd732118

2
riscv-tests

@ -1 +1 @@
Subproject commit 6fdd12c130d0c0c13934364a4dfe12d8dcf28e27 Subproject commit e5d9d1af2e54d50ff2756a8a868c6e7436739311

2
riscv-tools

@ -1 +1 @@
Subproject commit 76441991a8669da66b0d4a716fdbfdf846888684 Subproject commit 3338089dbd9da62784544b03630aa8df18bd89de

2
rocket

@ -1 +1 @@
Subproject commit 42f215b37a89037be2065ada25d078409f81bcdb Subproject commit 08cd734296ff1bf11695a0adc80077bad4d0b57d

4
src/main/scala/RocketChip.scala
View File

@ -257,9 +257,7 @@ class Top extends Module {
val vic = ICacheConfig(128, 1) val vic = ICacheConfig(128, 1)
val hc = hwacha.HwachaConfiguration(vic, 8, 256, ndtlb = 8, nptlb = 2) val hc = hwacha.HwachaConfiguration(vic, 8, 256, ndtlb = 8, nptlb = 2)
val rc = RocketConfiguration(tl, ic, dc, val rc = RocketConfiguration(tl, ic, dc,
fpu = HAS_FPU, fpu = HAS_FPU)
rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c))
)
val io = new VLSITopIO(HTIF_WIDTH) val io = new VLSITopIO(HTIF_WIDTH)