riscv/rocket-chip
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fix bug in RTC

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This commit is contained in:
Howard Mao 2016-03-24 18:09:37 -07:00
parent 00b3908d92
commit 11bd15432a
1 changed files with 1 additions and 1 deletions
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uncore/src/main/scala/rtc.scala
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@ -39,7 +39,7 @@ class RTC(csr_MTIME: Int)(implicit p: Parameters) extends HtifModule
coreId := addr_send_cnt coreId := addr_send_cnt
} else { } else {
when (io.aw.fire()) { sending_addr := Bool(false) } when (io.aw.fire()) { sending_addr := Bool(false) }
when (io.w.fire()) { sending_addr := Bool(false) } when (io.w.fire()) { sending_data := Bool(false) }
coreId := UInt(0) coreId := UInt(0)
} }