TileLinkIO.GrantAck -> TileLinkIO.Finish
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3f53d532c2
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@ -214,9 +214,9 @@ class L2HellaCache(bankId: Int)(implicit conf: L2CacheConfig) extends CoherenceA
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grant_arb.io.in zip trackerList map { case (arb, t) => arb <> t.io.client.grant }
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// Free finished transactions
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val ack = io.client.grant_ack
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trackerList.map(_.io.client.grant_ack.valid := ack.valid)
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trackerList.map(_.io.client.grant_ack.bits := ack.bits)
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val ack = io.client.finish
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trackerList.map(_.io.client.finish.valid := ack.valid)
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trackerList.map(_.io.client.finish.bits := ack.bits)
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ack.ready := Bool(true)
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// Create an arbiter for the one memory port
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@ -239,7 +239,7 @@ abstract class L2XactTracker()(implicit conf: L2CacheConfig) extends Module {
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val c_acq = io.client.acquire.bits
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val c_rel = io.client.release.bits
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val c_gnt = io.client.grant.bits
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val c_ack = io.client.grant_ack.bits
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val c_ack = io.client.finish.bits
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val m_gnt = io.master.grant.bits
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}
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@ -423,7 +423,7 @@ class L2AcquireTracker(trackerId: Int, bankId: Int)(implicit conf: L2CacheConfig
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when(io.master.grant.valid && m_gnt.payload.client_xact_id === UInt(trackerId)) {
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io.client.grant.valid := Bool(true)
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}
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when(io.client.grant_ack.valid && c_ack.payload.master_xact_id === UInt(trackerId)) {
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when(io.client.finish.valid && c_ack.payload.master_xact_id === UInt(trackerId)) {
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state := s_idle
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}
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}
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@ -154,7 +154,7 @@ class HTIF(w: Int, pcr_RESET: Int, nSCR: Int, offsetBits: Int)(implicit conf: Ti
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}
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mem_acked := Bool(false)
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}
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when (state === state_mem_finish && io.mem.grant_ack.ready) {
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when (state === state_mem_finish && io.mem.finish.ready) {
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state := Mux(cmd === cmd_readmem || pos === UInt(1), state_tx, state_rx)
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pos := pos - UInt(1)
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addr := addr + UInt(1 << offsetBits-3)
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@ -186,9 +186,9 @@ class HTIF(w: Int, pcr_RESET: Int, nSCR: Int, offsetBits: Int)(implicit conf: Ti
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io.mem.acquire.bits.payload.data := mem_req_data
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io.mem.acquire.bits.header.src := UInt(conf.ln.nClients) // By convention HTIF is the client with the largest id
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io.mem.acquire.bits.header.dst := UInt(0) // DNC; Overwritten outside module
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io.mem.grant_ack.valid := (state === state_mem_finish) && mem_needs_ack
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io.mem.grant_ack.bits.payload.master_xact_id := mem_gxid
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io.mem.grant_ack.bits.header.dst := mem_gsrc
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io.mem.finish.valid := (state === state_mem_finish) && mem_needs_ack
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io.mem.finish.bits.payload.master_xact_id := mem_gxid
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io.mem.finish.bits.header.dst := mem_gsrc
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io.mem.probe.ready := Bool(false)
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io.mem.release.valid := Bool(false)
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@ -148,14 +148,14 @@ class Grant(implicit val tlconf: TileLinkConfiguration) extends MasterSourcedMes
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val g_type = UInt(width = tlconf.co.grantTypeWidth)
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}
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class GrantAck(implicit val tlconf: TileLinkConfiguration) extends ClientSourcedMessage with HasMasterTransactionId
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class Finish(implicit val tlconf: TileLinkConfiguration) extends ClientSourcedMessage with HasMasterTransactionId
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class UncachedTileLinkIO(implicit conf: TileLinkConfiguration) extends Bundle {
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implicit val ln = conf.ln
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val acquire = new DecoupledIO(new LogicalNetworkIO(new Acquire))
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val grant = new DecoupledIO(new LogicalNetworkIO(new Grant)).flip
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val grant_ack = new DecoupledIO(new LogicalNetworkIO(new GrantAck))
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val finish = new DecoupledIO(new LogicalNetworkIO(new Finish))
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override def clone = { new UncachedTileLinkIO().asInstanceOf[this.type] }
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}
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@ -214,9 +214,9 @@ abstract class UncachedTileLinkIOArbiter(n: Int)(implicit conf: TileLinkConfigur
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hookupClientSource(io.in.map(_.acquire), io.out.acquire)
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hookupMasterSource(io.in.map(_.grant), io.out.grant)
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val grant_ack_arb = Module(new RRArbiter(new LogicalNetworkIO(new GrantAck), n))
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io.out.grant_ack <> grant_ack_arb.io.out
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grant_ack_arb.io.in zip io.in map { case (arb, req) => arb <> req.grant_ack }
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val finish_arb = Module(new RRArbiter(new LogicalNetworkIO(new Finish), n))
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io.out.finish <> finish_arb.io.out
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finish_arb.io.in zip io.in map { case (arb, req) => arb <> req.finish }
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}
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abstract class TileLinkIOArbiter(n: Int)(implicit conf: TileLinkConfiguration) extends TileLinkArbiterLike(n)(conf) {
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@ -233,9 +233,9 @@ abstract class TileLinkIOArbiter(n: Int)(implicit conf: TileLinkConfiguration) e
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io.in.map{ _.probe.bits := io.out.probe.bits }
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io.out.probe.ready := io.in.map(_.probe.ready).reduce(_||_)
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val grant_ack_arb = Module(new RRArbiter(new LogicalNetworkIO(new GrantAck), n))
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io.out.grant_ack <> grant_ack_arb.io.out
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grant_ack_arb.io.in zip io.in map { case (arb, req) => arb <> req.grant_ack }
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val finish_arb = Module(new RRArbiter(new LogicalNetworkIO(new Finish), n))
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io.out.finish <> finish_arb.io.out
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finish_arb.io.in zip io.in map { case (arb, req) => arb <> req.finish }
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}
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abstract trait AppendsArbiterId {
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@ -64,9 +64,9 @@ class L2CoherenceAgent(bankId: Int)(implicit conf: L2CoherenceAgentConfiguration
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grant_arb.io.in zip trackerList map { case (arb, t) => arb <> t.io.client.grant }
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// Free finished transactions
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val ack = io.client.grant_ack
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trackerList.map(_.io.client.grant_ack.valid := ack.valid)
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trackerList.map(_.io.client.grant_ack.bits := ack.bits)
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val ack = io.client.finish
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trackerList.map(_.io.client.finish.valid := ack.valid)
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trackerList.map(_.io.client.finish.bits := ack.bits)
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ack.ready := Bool(true)
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// Create an arbiter for the one memory port
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@ -89,7 +89,7 @@ abstract class XactTracker()(implicit conf: L2CoherenceAgentConfiguration) exten
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val c_acq = io.client.acquire.bits
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val c_rel = io.client.release.bits
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val c_gnt = io.client.grant.bits
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val c_ack = io.client.grant_ack.bits
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val c_ack = io.client.finish.bits
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val m_gnt = io.master.grant.bits
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}
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@ -273,7 +273,7 @@ class AcquireTracker(trackerId: Int, bankId: Int)(implicit conf: L2CoherenceAgen
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when(io.master.grant.valid && m_gnt.payload.client_xact_id === UInt(trackerId)) {
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io.client.grant.valid := Bool(true)
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}
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when(io.client.grant_ack.valid && c_ack.payload.master_xact_id === UInt(trackerId)) {
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when(io.client.finish.valid && c_ack.payload.master_xact_id === UInt(trackerId)) {
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state := s_idle
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}
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}
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