diff --git a/uncore/src/main/scala/cache.scala b/uncore/src/main/scala/cache.scala
index bd677c08..3af6f29f 100644
--- a/uncore/src/main/scala/cache.scala
+++ b/uncore/src/main/scala/cache.scala
@@ -214,9 +214,9 @@ class L2HellaCache(bankId: Int)(implicit conf: L2CacheConfig) extends CoherenceA
   grant_arb.io.in zip trackerList map { case (arb, t) => arb <> t.io.client.grant }
 
   // Free finished transactions
-  val ack = io.client.grant_ack
-  trackerList.map(_.io.client.grant_ack.valid := ack.valid)
-  trackerList.map(_.io.client.grant_ack.bits := ack.bits)
+  val ack = io.client.finish
+  trackerList.map(_.io.client.finish.valid := ack.valid)
+  trackerList.map(_.io.client.finish.bits := ack.bits)
   ack.ready := Bool(true)
 
   // Create an arbiter for the one memory port
@@ -239,7 +239,7 @@ abstract class L2XactTracker()(implicit conf: L2CacheConfig) extends Module {
   val c_acq = io.client.acquire.bits
   val c_rel = io.client.release.bits
   val c_gnt = io.client.grant.bits
-  val c_ack = io.client.grant_ack.bits
+  val c_ack = io.client.finish.bits
   val m_gnt = io.master.grant.bits
 
 }
@@ -423,7 +423,7 @@ class L2AcquireTracker(trackerId: Int, bankId: Int)(implicit conf: L2CacheConfig
       when(io.master.grant.valid && m_gnt.payload.client_xact_id === UInt(trackerId)) {
         io.client.grant.valid := Bool(true)
       }
-      when(io.client.grant_ack.valid && c_ack.payload.master_xact_id === UInt(trackerId)) {
+      when(io.client.finish.valid && c_ack.payload.master_xact_id === UInt(trackerId)) {
         state := s_idle
       }
     }
diff --git a/uncore/src/main/scala/htif.scala b/uncore/src/main/scala/htif.scala
index 9ea26f86..41d6df28 100644
--- a/uncore/src/main/scala/htif.scala
+++ b/uncore/src/main/scala/htif.scala
@@ -154,7 +154,7 @@ class HTIF(w: Int, pcr_RESET: Int, nSCR: Int, offsetBits: Int)(implicit conf: Ti
     }
     mem_acked := Bool(false)
   }
-  when (state === state_mem_finish && io.mem.grant_ack.ready) {
+  when (state === state_mem_finish && io.mem.finish.ready) {
     state := Mux(cmd === cmd_readmem || pos === UInt(1),  state_tx, state_rx)
     pos := pos - UInt(1)
     addr := addr + UInt(1 << offsetBits-3)
@@ -186,9 +186,9 @@ class HTIF(w: Int, pcr_RESET: Int, nSCR: Int, offsetBits: Int)(implicit conf: Ti
   io.mem.acquire.bits.payload.data := mem_req_data
   io.mem.acquire.bits.header.src := UInt(conf.ln.nClients) // By convention HTIF is the client with the largest id
   io.mem.acquire.bits.header.dst := UInt(0) // DNC; Overwritten outside module
-  io.mem.grant_ack.valid := (state === state_mem_finish) && mem_needs_ack
-  io.mem.grant_ack.bits.payload.master_xact_id := mem_gxid
-  io.mem.grant_ack.bits.header.dst := mem_gsrc
+  io.mem.finish.valid := (state === state_mem_finish) && mem_needs_ack
+  io.mem.finish.bits.payload.master_xact_id := mem_gxid
+  io.mem.finish.bits.header.dst := mem_gsrc
   io.mem.probe.ready := Bool(false)
   io.mem.release.valid := Bool(false)
 
diff --git a/uncore/src/main/scala/tilelink.scala b/uncore/src/main/scala/tilelink.scala
index 22941d29..68da8213 100644
--- a/uncore/src/main/scala/tilelink.scala
+++ b/uncore/src/main/scala/tilelink.scala
@@ -148,14 +148,14 @@ class Grant(implicit val tlconf: TileLinkConfiguration) extends MasterSourcedMes
   val g_type = UInt(width = tlconf.co.grantTypeWidth)
 }
 
-class GrantAck(implicit val tlconf: TileLinkConfiguration) extends ClientSourcedMessage with HasMasterTransactionId
+class Finish(implicit val tlconf: TileLinkConfiguration) extends ClientSourcedMessage with HasMasterTransactionId
 
 
 class UncachedTileLinkIO(implicit conf: TileLinkConfiguration) extends Bundle {
   implicit val ln = conf.ln
   val acquire   = new DecoupledIO(new LogicalNetworkIO(new Acquire))
   val grant     = new DecoupledIO(new LogicalNetworkIO(new Grant)).flip
-  val grant_ack = new DecoupledIO(new LogicalNetworkIO(new GrantAck))
+  val finish = new DecoupledIO(new LogicalNetworkIO(new Finish))
   override def clone = { new UncachedTileLinkIO().asInstanceOf[this.type] }
 }
 
@@ -214,9 +214,9 @@ abstract class UncachedTileLinkIOArbiter(n: Int)(implicit conf: TileLinkConfigur
   hookupClientSource(io.in.map(_.acquire), io.out.acquire)
   hookupMasterSource(io.in.map(_.grant), io.out.grant)
 
-  val grant_ack_arb = Module(new RRArbiter(new LogicalNetworkIO(new GrantAck), n))
-  io.out.grant_ack <> grant_ack_arb.io.out
-  grant_ack_arb.io.in zip io.in map { case (arb, req) => arb <> req.grant_ack }
+  val finish_arb = Module(new RRArbiter(new LogicalNetworkIO(new Finish), n))
+  io.out.finish <> finish_arb.io.out
+  finish_arb.io.in zip io.in map { case (arb, req) => arb <> req.finish }
 }
 
 abstract class TileLinkIOArbiter(n: Int)(implicit conf: TileLinkConfiguration) extends TileLinkArbiterLike(n)(conf) {
@@ -233,9 +233,9 @@ abstract class TileLinkIOArbiter(n: Int)(implicit conf: TileLinkConfiguration) e
   io.in.map{ _.probe.bits := io.out.probe.bits }
   io.out.probe.ready := io.in.map(_.probe.ready).reduce(_||_)
 
-  val grant_ack_arb = Module(new RRArbiter(new LogicalNetworkIO(new GrantAck), n))
-  io.out.grant_ack <> grant_ack_arb.io.out
-  grant_ack_arb.io.in zip io.in map { case (arb, req) => arb <> req.grant_ack }
+  val finish_arb = Module(new RRArbiter(new LogicalNetworkIO(new Finish), n))
+  io.out.finish <> finish_arb.io.out
+  finish_arb.io.in zip io.in map { case (arb, req) => arb <> req.finish }
 }
 
 abstract trait AppendsArbiterId {
diff --git a/uncore/src/main/scala/uncore.scala b/uncore/src/main/scala/uncore.scala
index 3e162583..0a3b7d6e 100644
--- a/uncore/src/main/scala/uncore.scala
+++ b/uncore/src/main/scala/uncore.scala
@@ -64,9 +64,9 @@ class L2CoherenceAgent(bankId: Int)(implicit conf: L2CoherenceAgentConfiguration
   grant_arb.io.in zip trackerList map { case (arb, t) => arb <> t.io.client.grant }
 
   // Free finished transactions
-  val ack = io.client.grant_ack
-  trackerList.map(_.io.client.grant_ack.valid := ack.valid)
-  trackerList.map(_.io.client.grant_ack.bits := ack.bits)
+  val ack = io.client.finish
+  trackerList.map(_.io.client.finish.valid := ack.valid)
+  trackerList.map(_.io.client.finish.bits := ack.bits)
   ack.ready := Bool(true)
 
   // Create an arbiter for the one memory port
@@ -89,7 +89,7 @@ abstract class XactTracker()(implicit conf: L2CoherenceAgentConfiguration) exten
   val c_acq = io.client.acquire.bits
   val c_rel = io.client.release.bits
   val c_gnt = io.client.grant.bits
-  val c_ack = io.client.grant_ack.bits
+  val c_ack = io.client.finish.bits
   val m_gnt = io.master.grant.bits
 
 }
@@ -273,7 +273,7 @@ class AcquireTracker(trackerId: Int, bankId: Int)(implicit conf: L2CoherenceAgen
       when(io.master.grant.valid && m_gnt.payload.client_xact_id === UInt(trackerId)) {
         io.client.grant.valid := Bool(true)
       }
-      when(io.client.grant_ack.valid && c_ack.payload.master_xact_id === UInt(trackerId)) {
+      when(io.client.finish.valid && c_ack.payload.master_xact_id === UInt(trackerId)) {
         state := s_idle
       }
     }