riscv/rocket-chip
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Use more parsimonious queue depths

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This commit is contained in:
Andrew Waterman 2016-05-26 18:04:22 -07:00
parent 3cc236e9c4
commit 10f0e13c25
1 changed files with 6 additions and 6 deletions
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12
src/main/scala/RocketChip.scala
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@ -87,11 +87,11 @@ object TopUtils {
// Connect two Nasti interfaces with queues in-between // Connect two Nasti interfaces with queues in-between
def connectNasti(outer: NastiIO, inner: NastiIO)(implicit p: Parameters) { def connectNasti(outer: NastiIO, inner: NastiIO)(implicit p: Parameters) {
val mifDataBeats = p(MIFDataBeats) val mifDataBeats = p(MIFDataBeats)
outer.ar <> Queue(inner.ar) outer.ar <> Queue(inner.ar, 1)
outer.aw <> Queue(inner.aw) outer.aw <> Queue(inner.aw, 1)
outer.w <> Queue(inner.w, mifDataBeats) outer.w <> Queue(inner.w)
inner.r <> Queue(outer.r, mifDataBeats) inner.r <> Queue(outer.r)
inner.b <> Queue(outer.b) inner.b <> Queue(outer.b, 1)
} }
def connectTilelinkNasti(nasti: NastiIO, tl: ClientUncachedTileLinkIO)(implicit p: Parameters) = { def connectTilelinkNasti(nasti: NastiIO, tl: ClientUncachedTileLinkIO)(implicit p: Parameters) = {
val conv = Module(new NastiIOTileLinkIOConverter()) val conv = Module(new NastiIOTileLinkIOConverter())
@ -272,7 +272,7 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
if (nBanks > 1) addr(lsb + log2Up(nBanks) - 1, lsb) else UInt(0), if (nBanks > 1) addr(lsb + log2Up(nBanks) - 1, lsb) else UInt(0),
UInt(nBanks)) UInt(nBanks))
} }
val preBuffering = TileLinkDepths(2,2,2,2,2) val preBuffering = TileLinkDepths(1,1,2,2,0)
val l1tol2net = Module(new PortedTileLinkCrossbar(addrToBank, sharerToClientId, preBuffering)) val l1tol2net = Module(new PortedTileLinkCrossbar(addrToBank, sharerToClientId, preBuffering))
// Create point(s) of coherence serialization // Create point(s) of coherence serialization