riscv/rocket-chip
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fix mul/div to rd=0

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This commit is contained in:
Andrew Waterman 2012-02-08 20:11:57 -08:00
parent a1855b12c2
commit 10b5a0006c
1 changed files with 2 additions and 2 deletions
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4
rocket/src/main/scala/ctrl.scala
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@ -334,8 +334,8 @@ class rocketCtrl extends Component
otherwise { otherwise {
ex_reg_br_type <== id_br_type; ex_reg_br_type <== id_br_type;
ex_reg_btb_hit <== id_reg_btb_hit; ex_reg_btb_hit <== id_reg_btb_hit;
ex_reg_div_val <== id_div_val.toBool; ex_reg_div_val <== id_div_val.toBool && id_waddr != UFix(0);
ex_reg_mul_val <== id_mul_val.toBool; ex_reg_mul_val <== id_mul_val.toBool && id_waddr != UFix(0);
ex_reg_mem_val <== id_mem_val.toBool; ex_reg_mem_val <== id_mem_val.toBool;
ex_reg_wen <== id_wen.toBool && id_waddr != UFix(0); ex_reg_wen <== id_wen.toBool && id_waddr != UFix(0);
ex_reg_fp_wen <== fpdec.io.wen; ex_reg_fp_wen <== fpdec.io.wen;