make sure L1 and L2 agree on coherence policy
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6a5b2d7f59
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1063d90993
@ -254,11 +254,12 @@ class BaseConfig extends Config (
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HastiParameters(
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addrBits = site(PAddrBits),
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dataBits = site(XLen))
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case TLKey("L1toL2") =>
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case TLKey("L1toL2") => {
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val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
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TileLinkParameters(
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coherencePolicy = (if (site(NCachedTileLinkPorts) <= 1)
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new MEICoherence(site(L2DirectoryRepresentation)) else
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new MESICoherence(site(L2DirectoryRepresentation))),
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coherencePolicy = (
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if (useMEI) new MEICoherence(site(L2DirectoryRepresentation))
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else new MESICoherence(site(L2DirectoryRepresentation))),
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nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1 /* MMIO */,
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nCachingClients = site(NCachedTileLinkPorts),
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nCachelessClients = site(NExtBusAXIChannels) + site(NUncachedTileLinkPorts),
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@ -271,6 +272,7 @@ class BaseConfig extends Config (
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maxManagerXacts = site(NAcquireTransactors) + 2,
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dataBeats = innerDataBeats,
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dataBits = site(CacheBlockBytes)*8)
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}
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case TLKey("L2toMC") =>
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TileLinkParameters(
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coherencePolicy = new MEICoherence(
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@ -17,11 +17,12 @@ import ConfigUtils._
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class WithGroundTest extends Config(
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(pname, site, here) => pname match {
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case TLKey("L1toL2") =>
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case TLKey("L1toL2") => {
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val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
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TileLinkParameters(
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coherencePolicy = (if (site(NCachedTileLinkPorts) <= 1)
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new MEICoherence(site(L2DirectoryRepresentation)) else
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new MESICoherence(site(L2DirectoryRepresentation))),
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coherencePolicy = (
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if (useMEI) new MEICoherence(site(L2DirectoryRepresentation))
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else new MESICoherence(site(L2DirectoryRepresentation))),
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nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1,
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nCachingClients = site(NCachedTileLinkPorts),
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nCachelessClients = site(NUncachedTileLinkPorts),
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@ -32,6 +33,7 @@ class WithGroundTest extends Config(
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maxManagerXacts = site(NAcquireTransactors) + 2,
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dataBeats = 8,
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dataBits = site(CacheBlockBytes)*8)
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}
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case BuildTiles => {
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val groundtest = if (site(XLen) == 64)
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DefaultTestSuites.groundtest64
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