diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index 6d7e29fa..6ef82984 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -254,11 +254,12 @@ class BaseConfig extends Config (
         HastiParameters(
           addrBits = site(PAddrBits),
           dataBits = site(XLen))
-      case TLKey("L1toL2") =>
+      case TLKey("L1toL2") => {
+        val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
         TileLinkParameters(
-          coherencePolicy = (if (site(NCachedTileLinkPorts) <= 1)
-            new MEICoherence(site(L2DirectoryRepresentation)) else
-              new MESICoherence(site(L2DirectoryRepresentation))),
+          coherencePolicy = (
+            if (useMEI) new MEICoherence(site(L2DirectoryRepresentation))
+            else new MESICoherence(site(L2DirectoryRepresentation))),
           nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1 /* MMIO */,
           nCachingClients = site(NCachedTileLinkPorts),
           nCachelessClients = site(NExtBusAXIChannels) + site(NUncachedTileLinkPorts),
@@ -271,6 +272,7 @@ class BaseConfig extends Config (
           maxManagerXacts = site(NAcquireTransactors) + 2,
           dataBeats = innerDataBeats,
           dataBits = site(CacheBlockBytes)*8)
+      }
       case TLKey("L2toMC") => 
         TileLinkParameters(
           coherencePolicy = new MEICoherence(
diff --git a/src/main/scala/TestConfigs.scala b/src/main/scala/TestConfigs.scala
index 0681e30a..81098131 100644
--- a/src/main/scala/TestConfigs.scala
+++ b/src/main/scala/TestConfigs.scala
@@ -17,11 +17,12 @@ import ConfigUtils._
 
 class WithGroundTest extends Config(
   (pname, site, here) => pname match {
-    case TLKey("L1toL2") =>
+    case TLKey("L1toL2") => {
+      val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
       TileLinkParameters(
-        coherencePolicy = (if (site(NCachedTileLinkPorts) <= 1)
-          new MEICoherence(site(L2DirectoryRepresentation)) else
-            new MESICoherence(site(L2DirectoryRepresentation))),
+        coherencePolicy = (
+          if (useMEI) new MEICoherence(site(L2DirectoryRepresentation))
+          else new MESICoherence(site(L2DirectoryRepresentation))),
         nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1,
         nCachingClients = site(NCachedTileLinkPorts),
         nCachelessClients = site(NUncachedTileLinkPorts),
@@ -32,6 +33,7 @@ class WithGroundTest extends Config(
         maxManagerXacts = site(NAcquireTransactors) + 2,
         dataBeats = 8,
         dataBits = site(CacheBlockBytes)*8)
+    }
     case BuildTiles => {
       val groundtest = if (site(XLen) == 64)
         DefaultTestSuites.groundtest64