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make sure L1 and L2 agree on coherence policy

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This commit is contained in:
Howard Mao 2016-07-25 12:20:49 -07:00
parent 6a5b2d7f59
commit 1063d90993
2 changed files with 12 additions and 8 deletions
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10
src/main/scala/Configs.scala
View File

@ -254,11 +254,12 @@ class BaseConfig extends Config (
HastiParameters( HastiParameters(
addrBits = site(PAddrBits), addrBits = site(PAddrBits),
dataBits = site(XLen)) dataBits = site(XLen))
case TLKey("L1toL2") => case TLKey("L1toL2") => {
val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
TileLinkParameters( TileLinkParameters(
coherencePolicy = (if (site(NCachedTileLinkPorts) <= 1) coherencePolicy = (
new MEICoherence(site(L2DirectoryRepresentation)) else if (useMEI) new MEICoherence(site(L2DirectoryRepresentation))
new MESICoherence(site(L2DirectoryRepresentation))), else new MESICoherence(site(L2DirectoryRepresentation))),
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1 /* MMIO */, nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1 /* MMIO */,
nCachingClients = site(NCachedTileLinkPorts), nCachingClients = site(NCachedTileLinkPorts),
nCachelessClients = site(NExtBusAXIChannels) + site(NUncachedTileLinkPorts), nCachelessClients = site(NExtBusAXIChannels) + site(NUncachedTileLinkPorts),
@ -271,6 +272,7 @@ class BaseConfig extends Config (
maxManagerXacts = site(NAcquireTransactors) + 2, maxManagerXacts = site(NAcquireTransactors) + 2,
dataBeats = innerDataBeats, dataBeats = innerDataBeats,
dataBits = site(CacheBlockBytes)*8) dataBits = site(CacheBlockBytes)*8)
}
case TLKey("L2toMC") => case TLKey("L2toMC") =>
TileLinkParameters( TileLinkParameters(
coherencePolicy = new MEICoherence( coherencePolicy = new MEICoherence(

10
src/main/scala/TestConfigs.scala
View File

@ -17,11 +17,12 @@ import ConfigUtils._
class WithGroundTest extends Config( class WithGroundTest extends Config(
(pname, site, here) => pname match { (pname, site, here) => pname match {
case TLKey("L1toL2") => case TLKey("L1toL2") => {
val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
TileLinkParameters( TileLinkParameters(
coherencePolicy = (if (site(NCachedTileLinkPorts) <= 1) coherencePolicy = (
new MEICoherence(site(L2DirectoryRepresentation)) else if (useMEI) new MEICoherence(site(L2DirectoryRepresentation))
new MESICoherence(site(L2DirectoryRepresentation))), else new MESICoherence(site(L2DirectoryRepresentation))),
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1, nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1,
nCachingClients = site(NCachedTileLinkPorts), nCachingClients = site(NCachedTileLinkPorts),
nCachelessClients = site(NUncachedTileLinkPorts), nCachelessClients = site(NUncachedTileLinkPorts),
@ -32,6 +33,7 @@ class WithGroundTest extends Config(
maxManagerXacts = site(NAcquireTransactors) + 2, maxManagerXacts = site(NAcquireTransactors) + 2,
dataBeats = 8, dataBeats = 8,
dataBits = site(CacheBlockBytes)*8) dataBits = site(CacheBlockBytes)*8)
}
case BuildTiles => { case BuildTiles => {
val groundtest = if (site(XLen) == 64) val groundtest = if (site(XLen) == 64)
DefaultTestSuites.groundtest64 DefaultTestSuites.groundtest64