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make sure L1 and L2 agree on coherence policy

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This commit is contained in:
Howard Mao
2016-07-25 12:20:49 -07:00
parent 6a5b2d7f59
commit 1063d90993
2 changed files with 12 additions and 8 deletions
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10
src/main/scala/Configs.scala
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@ -254,11 +254,12 @@ class BaseConfig extends Config (
HastiParameters(
addrBits = site(PAddrBits),
dataBits = site(XLen))
case TLKey("L1toL2") =>
case TLKey("L1toL2") => {
val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
TileLinkParameters(
coherencePolicy = (if (site(NCachedTileLinkPorts) <= 1)
new MEICoherence(site(L2DirectoryRepresentation)) else
new MESICoherence(site(L2DirectoryRepresentation))),
coherencePolicy = (
if (useMEI) new MEICoherence(site(L2DirectoryRepresentation))
else new MESICoherence(site(L2DirectoryRepresentation))),
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1 /* MMIO */,
nCachingClients = site(NCachedTileLinkPorts),
nCachelessClients = site(NExtBusAXIChannels) + site(NUncachedTileLinkPorts),
@ -271,6 +272,7 @@ class BaseConfig extends Config (
maxManagerXacts = site(NAcquireTransactors) + 2,
dataBeats = innerDataBeats,
dataBits = site(CacheBlockBytes)*8)
}
case TLKey("L2toMC") =>
TileLinkParameters(
coherencePolicy = new MEICoherence(