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tilelink2 RegisterRouter: data path register is no longer required

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This commit is contained in:
Wesley W. Terpstra 2016-10-12 18:10:07 -07:00
parent c4eadd3ab3
commit 0e897b905f
1 changed files with 2 additions and 4 deletions
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6
src/main/scala/uncore/tilelink2/RegisterRouter.scala
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@ -41,10 +41,8 @@ class TLRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int =
in.bits.mask := a.bits.mask in.bits.mask := a.bits.mask
in.bits.extra := Cat(edge.addr_lo(a.bits), a.bits.source, a.bits.size) in.bits.extra := Cat(edge.addr_lo(a.bits), a.bits.source, a.bits.size)
// Invoke the register map builder and make it Irrevocable // Invoke the register map builder
val out = Queue.irrevocable( val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*)
RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*),
entries = 1, flow = true)
// No flow control needed // No flow control needed
in.valid := a.valid in.valid := a.valid