From 0e897b905f0d5dd91d7d17d08e61447262e10465 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 12 Oct 2016 18:10:07 -0700 Subject: [PATCH] tilelink2 RegisterRouter: data path register is no longer required --- src/main/scala/uncore/tilelink2/RegisterRouter.scala | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/main/scala/uncore/tilelink2/RegisterRouter.scala b/src/main/scala/uncore/tilelink2/RegisterRouter.scala index 89c62021..e414eb92 100644 --- a/src/main/scala/uncore/tilelink2/RegisterRouter.scala +++ b/src/main/scala/uncore/tilelink2/RegisterRouter.scala @@ -41,10 +41,8 @@ class TLRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = in.bits.mask := a.bits.mask in.bits.extra := Cat(edge.addr_lo(a.bits), a.bits.source, a.bits.size) - // Invoke the register map builder and make it Irrevocable - val out = Queue.irrevocable( - RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*), - entries = 1, flow = true) + // Invoke the register map builder + val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*) // No flow control needed in.valid := a.valid