riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

always merge Puts

Browse Source
This commit is contained in:
Henry Cook
2015-03-17 20:53:27 -07:00
parent d48775eecb
commit 0e4cf74d8a
1 changed files with 4 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
uncore/src/main/scala/cache.scala
View File

@@ -173,7 +173,6 @@ abstract trait L2HellaCacheParameters extends CacheParameters with CoherenceAgen
require(rowBits == innerDataBits) // TODO: relax this by improving s_data_* states
val nSecondaryMisses = 4
val enableGetMerging = false
val enablePutMerging = true
}
abstract class L2HellaCacheBundle extends Bundle with L2HellaCacheParameters
@@ -709,9 +708,8 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
do_allocate &&
ignt_q.io.enq.ready
//TODO: mix Puts and PutBlocks
val can_merge_iacq_put = ((Bool(enablePutMerging) &&
(xact.isBuiltInType(Acquire.putType) &&
io.iacq().isBuiltInType(Acquire.putType))) ||
val can_merge_iacq_put = ((xact.isBuiltInType(Acquire.putType) &&
io.iacq().isBuiltInType(Acquire.putType)) ||
(xact.isBuiltInType(Acquire.putBlockType) &&
io.iacq().isBuiltInType(Acquire.putBlockType))) &&
(xact_src === io.inner.acquire.bits.header.src) &&