riscv/rocket-chip
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always merge Puts

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This commit is contained in:
Henry Cook 2015-03-17 20:53:27 -07:00
parent d48775eecb
commit 0e4cf74d8a
1 changed files with 4 additions and 6 deletions
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6
uncore/src/main/scala/cache.scala
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@ -173,7 +173,6 @@ abstract trait L2HellaCacheParameters extends CacheParameters with CoherenceAgen
require(rowBits == innerDataBits) // TODO: relax this by improving s_data_* states require(rowBits == innerDataBits) // TODO: relax this by improving s_data_* states
val nSecondaryMisses = 4 val nSecondaryMisses = 4
val enableGetMerging = false val enableGetMerging = false
val enablePutMerging = true
} }
abstract class L2HellaCacheBundle extends Bundle with L2HellaCacheParameters abstract class L2HellaCacheBundle extends Bundle with L2HellaCacheParameters
@ -709,9 +708,8 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
do_allocate && do_allocate &&
ignt_q.io.enq.ready ignt_q.io.enq.ready
//TODO: mix Puts and PutBlocks //TODO: mix Puts and PutBlocks
val can_merge_iacq_put = ((Bool(enablePutMerging) && val can_merge_iacq_put = ((xact.isBuiltInType(Acquire.putType) &&
(xact.isBuiltInType(Acquire.putType) && io.iacq().isBuiltInType(Acquire.putType)) ||
io.iacq().isBuiltInType(Acquire.putType))) ||
(xact.isBuiltInType(Acquire.putBlockType) && (xact.isBuiltInType(Acquire.putBlockType) &&
io.iacq().isBuiltInType(Acquire.putBlockType))) && io.iacq().isBuiltInType(Acquire.putBlockType))) &&
(xact_src === io.inner.acquire.bits.header.src) && (xact_src === io.inner.acquire.bits.header.src) &&